LM3S608-IQC20-B0 Просмотр технического описания (PDF) - Unspecified

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LM3S608-IQC20-B0

LM3S608 Microcontroller

Unspecified 

Architectural Overview

– 32 KB single-cycle flash

• User-managed flash block protection on a 2-KB block basis

• User-managed flash data programming

• User-defined and managed flash-protection block

– 8 KB single-cycle SRAM

■ General-Purpose Timers

– Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit

timer/counters. Each GPTM can be configured to operate independently as timers or event

counters: as a single 32-bit timer, as one 32-bit Real-Time Clock (RTC) to event capture, for

Pulse Width Modulation (PWM), or to trigger analog-to-digital conversions

– 32-bit Timer modes

• Programmable one-shot timer

• Programmable periodic timer

• Real-Time Clock when using an external 32.768-KHz clock as the input

• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU

Halt flag during debug

• ADC event trigger

– 16-bit Timer modes

• General-purpose timer function with an 8-bit prescaler

• Programmable one-shot timer

• Programmable periodic timer

• User-enabled stalling when the controller asserts CPU Halt flag during debug

• ADC event trigger

– 16-bit Input Capture modes

• Input edge count capture

• Input edge time capture

– 16-bit PWM mode

• Simple PWM mode with software-programmable output inversion of the PWM signal

■ ARM FiRM-compliant Watchdog Timer

– 32-bit down counter with a programmable load register

– Separate watchdog clock with an enable

20

October 01, 2007

Preliminary

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