LTC1273ACS Просмотр технического описания (PDF) - Linear Technology

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LTC1273ACS

12-Bit, 300ksps Sampling A/D Converters with Reference

Linear Technology 

LTC1273

LTC1275/LTC1276

APPLICATI S I FOR ATIO

TMS320C25

Figure 17 shows an interface between the LTC1273 and

the TMS320C25.

The W/R signal of the DSP initiates a conversion and

conversion results are read from the LTC1273 using the

following instruction:

IN D, PA

where D is Data Memory Address and PA is the PORT

ADDRESS.

A23

A1

ADDRESS BUS

AS

MC68000

DTACK

R/W

D11

D0

EN

ADDRESS

DECODE

DATA BUS

ADDITIONAL PINS OMITTED FOR CLARITY

LTC1273/75/76

CS

BUSY

RD

D11

D0/8 HBEN

LTC1273/75/76 • F18

A16

A1

ADDRESS BUS

Figure 18. MC68000 Interface

IS

TMS320C25

READY

R/W

D16

D0

EN

ADDRESS

DECODE

DATA BUS

LTC1273/75/76

CS

BUSY

RD

D11

D0/8 HBEN

ADDITIONAL PINS OMITTED FOR CLARITY

LTC1273/75/76 • F17

Figure 17. TMS320C25 Interface

MC68000 Microprocessor

Figure 18 shows a typical interface for the MC68000. The

LTC1273 is operating in the Slow Memory Mode. Assum-

ing the LTC1273 is located at address C000, then the

following single 16-bit MOVE instruction both starts a

conversion and reads the conversion result:

Move.W $C000,D0

At the beginning of the instruction cycle when the ADC

address is selected, BUSY and CS assert DTACK so that

the MC68000 is forced into a WAIT state. At the end of

conversion, BUSY returns high and the conversion result

is placed in the D0 register of the microprocessor.

8085A/Z80 Microprocessor

Figure 19 shows an LTC1273 interface for the Z80/8085A.

The LTC1273 is operating in the Slow Memory Mode and

a two byte read is required. Not shown in the figure is the

8-bit latch required to demultiplex the 8085A common

address/data bus. A0 is used to assert HBEN so that an

even address (HBEN = LOW) to the LTC1273 will start a

conversion and read the low data byte. An odd address

(HBEN = HIGH) will read the high data byte. This is

accomplished with the single 16-bit LOAD instruction

below.

For the 8085A

For the Z80

LHLD (B000)

LDHL, (B000)

A15

A0

MREQ

Z80

8085A

WAIT

RD

D7

D0

ADDRESS BUS

EN

ADDRESS

DECODE

DATA BUS

A0

HBEN

CS

BUSY

LTC1273/75/76

RD

D7

D0/8

ADDITIONAL PINS OMITTED FOR CLARITY

LTC1273/75/76 • F19

Figure 19. 8085A and Z80 Interface

19

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