LTC1699EGN-82 Просмотр технического описания (PDF) - Linear Technology
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LTC1699EGN-82 Datasheet PDF : 20 Pages
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LTC1699 Series
APPLICATIO S I FOR ATIO
SLAVE
ADDRESS
ON
COMMAND
S 1110001 R/W A 000XXXXX A
DATA LOW
(REGISTER 0)
DON’T CARE
A
DATA HIGH
(REGISTER 1)
DON’T CARE
AP
SLAVE
ADDRESS
OFF
COMMAND
S 1110001 R/W A 011XXXXX A
DATA LOW
(REGISTER 0)
DON’T CARE
A
DATA HIGH
(REGISTER 1)
DON’T CARE
UPDATE DCON
AP
SLAVE
ADDRESS
SETUP
COMMAND
DATA LOW
(REGISTER 0)
DATA HIGH
(REGISTER 1)
UPDATE DCON
S 1110001 R/W A 001XXXXX A VID4 VID3 VID2 VID1 VID0 X X X A VID4 VID3 VID2 VID1 VID0 X X X A P
COMMAND
LATCHED
DATA LOW
LATCHED
DATA HIGH UPDATE DCON
LATCHED
SLAVE
ADDRESS
READ-BACK
COMMAND
DATA LOW
(REGISTER 0)
DATA HIGH
(REGISTER 1)
S 1110001 R/W A 010XXXXX A S 1110010 RD A VID4 VID3 VID2 VID1 VID0 DCON 0 0 A VID4 VID3 VID2 VID1 VID0 DCON 0 0 A P
COMMAND
LATCHED
DATA LOW
LOADED
DATA HIGH
LOADED
Figure 2. Write Word and Read Word Protocols
STOP
(IGNORED)
Table 2. LTC1699-80, LTC1699-81 and LTC1699-82
Command Bits
C7
C6
C5
COMMAND
PROTOCOL
0
0
0
On
Write Word
0
1
1
Off
Write Word
0
0
1
Setup
Write Word
0
1
0
Read-Back
Read Word
Write Word Protocol
Each Write Word protocol (Figure 2) begins with a start bit
(S) and ends with a stop bit (P). As shown in the Timing
Diagram the start and stop bits are defined as high to low
and low to high transitions respectively, while SCL is high.
In between the start and stop bits, the microprocessor
transmits four bytes to the LTC1699-80, LTC1699-81 or
LTC1699-82. These are the address byte, an 8-bit com-
mand code and two data bytes. The LTC1699-80,
LTC1699-81 and LTC1699-82 sample each bit at the rising
edges of the SCL clock.
When the microprocessor issues a start bit, all the slave
devices on the bus, including the LTC1699-80, LTC1699-81
or LTC1699-82 clock in the address byte, which consists
of a 7-bit slave address and the R/W bit (set to 0). If the
slave address from the microprocessor does not match
the internal hardwired address, the LTC1699-80,
LTC1699-81 or LTC1699-82 returns to an idle state and
waits for the next start bit. If the slave address matches,
the LTC1699-80, LTC1699-81 or LTC1699-82 acknowl-
edges by pulling the SDA line low for one clock cycle after
the address byte. After detecting the acknowledgement bit
(A), the microprocessor transmits the second byte or
command code. The command code identifies the type of
Write Word protocol as Setup, On or Off (Table 2). The
Setup protocol is used to load two resistor divider settings
into Register 0 and 1. The On and Off protocols turn the
converters on or off in conjunction with the VRON pin.
Once all 8 bits of the command code are clocked in, the
LTC1699-80, LTC1699-81 or LTC1699-82 issues a sec-
ond acknowledgement bit to the microprocessor. After
detecting the acknowledgement bit, the microprocessor
transmits two data bytes. Each data byte is acknowledged
in turn for all three Write Word protocols but is only
latched into Register 0 or 1 in Setup protocol. This
prevents previously loaded settings from accidentally
being changed. The first or Data Low byte is loaded into
Register 0. The second or Data High byte is loaded into
12
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