LTC4090EDJC-TRPBF Просмотр технического описания (PDF) - Linear Technology
Номер в каталоге
Компоненты Описание
производитель
LTC4090EDJC-TRPBF Datasheet PDF : 30 Pages
| |||
LTC4090/LTC4090-5
APPLICATIONS INFORMATION
by calculating the regulator power loss from an efficiency
measurement, and subtracting the catch diode loss.
( ) PD = (1– h) •
5V • (IBAT +IOUT )
–
VD
•
1–
5V
VHVIN
•
(IBAT +IOUT ) + (5V – VBAT ) •IBAT
The difference between this equation and that for the
LTC4090 is the last term, which represents the power
dissipation in the battery charger. For a typical application,
an example of this calculation would be:
PD
=
(1–
0.87)
•
(5V
•
(1A
+ 0.6A ))
–
0.4V
•
1–
5V
12V
•
(1A +0.6A) +(5V – 3.7V) •1A = 1.97W
Like the LTC4090 example, this examples assumes 87%
efficiency, VHVIN = 12V, VBAT = 3.7V, IBAT = 1A and IOUT
= 600mA resulting in about 2W total power dissipation.
It is important to solder the exposed backside of the pack-
age to a ground plane. This ground should be tied to other
copper layers below with thermal vias; these layers will
spread the heat dissipated by the LTC4090/LTC4090-5.
Additional vias should be placed near the catch diode.
Adding more copper to the top and bottom layers and
tying this copper to the internal planes with vias can
C1 AND D1
GND PADS
SIDE-BY-SIDE
AND SEPERATED
WITH C3 GND PAD
MINIMIZE D1, L1,
C3, U1, SW PIN LOOP
reduce thermal resistance further. With these steps, the
thermal resistance from die (i.e., junction) to ambient can
be reduced to qJA = 40°C/W.
Board Layout Considerations
As discussed in the previous section, it is critical that
the exposed metal pad on the backside of the LTC4090/
LTC4090-5 package be soldered to the PC board ground.
Furthermore, proper operation and minimum EMI requires
a careful printed circuit board (PCB) layout. Note that large,
switched currents flow in the power switch (between the
HVIN and SW pins), the catch diode and the HVIN input
capacitor. These components, along with the inductor and
output capacitor, should be placed on the same side of
the circuit board, and their connections should be made
on that layer. Place a local, unbroken ground plane below
these components. The loop formed by these components
should be as small as possible.
Additionally, the SW and BOOST nodes should be kept
as small as possible. Figure 10 shows the recommended
component placement with trace and via locations.
High frequency currents, such as the high voltage input
current of the LTC4090/LTC4090-5, tend to find their way
along the ground plane on a mirror path directly beneath
the incident path on the top of the board. If there are slits
or cuts in the ground plane due to other traces on that
layer, the current will be forced to go around the slits.
If high frequency currents are not allowed to flow back
through their natural least-area path, excessive voltage will
build up and radiated emissions will occur. See Figure 11.
U1 THERMAL PAD
SOLDERED TO PCB.
VIAS CONNECTED TO ALL
GND PLANES WITHOUT
THERMAL RELIEF
MINIMIZE TRACE LENGTH
4090 F10
Figure 10. Suggested Board Layout
4090 F11
Figure 11. Ground Currents Follow Their Incident
Path at High Speed. Slices in the Ground Plane
Cause High Voltage and Increased Emissions.
4090fd
For more information www.linear.com/LTC4090
25
Share Link: 