M5M5V216ART-55LW Просмотр технического описания (PDF) - Mitsumi
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M5M5V216ART-55LW Datasheet PDF : 7 Pages
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revision-01, ' 98.12.08
M5M5V216ATP,RT
MITSUBISHI LSIs
(4)TIMING DIAGRAMS
Read cycle
A0~16
BC1
and / or
BC2
S
OE
W = "H" level
DQ1~16
(Note3)
(Note3)
(Note3)
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
tCR
ta(A)
ta(BC1) or ta(BC2)
tv (A)
ta(S)
ta (OE)
ten (OE)
ten (BC1)
ten (BC2)
ten (S)
tdis (BC1) or tdis (BC1)
tdis (S)
tdis (OE)
VALID DATA
(Note3)
(Note3)
(Note3)
Write cycle ( W control mode )
tCW
A0~16
BC1
and / or
BC2
S
(Note3)
(Note3)
tsu (BC1) or tsu(BC2)
tsu (S)
tsu (A-WH)
(Note3)
(Note3)
OE
W
DQ1~16
tsu (A)
tdis(OE)
tw (W)
tdis (W)
DATA IN
STABLE
tsu (D) th (D)
trec (W)
ten(OE)
ten (W)
MITSUBISHI ELECTRIC
5
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