5962-9161709Q9A Просмотр технического описания (PDF) - Atmel Corporation
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5962-9161709Q9A Datasheet PDF : 27 Pages
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AC Busy Characteristics
Table 9. AC Electrical Characteristics
Over the Full Operating Temperature and Supply Voltage Range
M
67025-30
M
67025-45
Write Cycle
Parameter
Min.
Max.
Min.
Max.
Unit
Busy Timing (For Master 67025 only)
tBAA
BUSY Access time
to address
–
30
–
35
ns
tBDA
BUSY Disable time
to address
–
25
–
30
ns
tBAC
BUSY Access time
to Chip Select
–
25
–
30
ns
tBDC
tWDD
tDDD
tAPS
tBDD
tWB
tWH
tWDD
tDDD
BUSY Disable time
to Chip Select
Write Pulse to data Delay (1)
Write data valid to read data delay(1)
Arbitration priority set-up time (2)
BUSY disable to valid data
Write to BUSY input (4)
Write hold after BUSY (5)
Write pulse to data delay (6)
Write data valid to read data delay(6)
–
20
–
25
ns
–
55
–
70
ns
–
40
–
55
ns
5
–
5
–
ns
–
(3)
–
(3)
ns
0
–
0
–
ns
20
–
25
–
ns
–
55
–
70
ns
–
40
–
55
ns
1.
Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Read with BUSY (For Mas-
ter 67025 only)’.
2.
To ensure that the earlier of the two ports wins.
3.
tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) to tDDD - tDW (actual).
4.
To ensure that the write cycle is inhibited during contention.
5.
To ensure that a write cycle is completed after contention.
6.
Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveforms of Read with Port-to-port
delay (For Slave, 67025 only)’.
17 M67025E
4146J–AERO–06/03
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