WAVEFORMS (Continued)
MINIMUM MODE (Continued)
M80C86 M80C86-2
271058 – 6
NOTES
1 All output timing measurements are made at 1 5V
2 RDY is sampled near the end of T2 T3 TW to determine if TW machines states are to be inserted
3 Two INTA cycles run back-to-back The M80C86 local ADDR DATA BUS is floating during both INTA cycles Control
signals shown for second INTA cycle
4 Signals at M82C84A are shown for reference only
13