MAX8529 Просмотр технического описания (PDF) - Maxim Integrated

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производитель

MAX8529

1.5MHz Dual 180° Out-of-Phase PWM Step-Down Controller with POR

Maxim Integrated 

1.5MHz Dual 180° Out-of-Phase

PWM Step-Down Controller with POR

MAX8529

OSC

CK0

SYNC

VL

MASTER

MAX8529

SYNC

SLAVE

MAX8529

CK0

OSC

SYNC

VL

MASTER

MAX8529

SYNC

OSC

SLAVE

2-PHASE SYSTEM

180° PHASE SHIFT

DH1

MASTER

DH2

DH1

SLAVE

DH2

4-PHASE SYSTEM

90° PHASE SHIFT

DH1

MASTER

DH2

DH1

SLAVE

DH2

Figure 5. Synchronized Controllers

Design Procedure

Effective Input Voltage Range

Although the MAX8529 controllers can operate from

input supplies ranging from 4.75V to 23V, the input

voltage range can be effectively limited by the

MAX8529’s duty-cycle limitations. The maximum input

voltage is limited by the minimum on-time (tON(MIN)):

VIN(MAX)

≤

VOUT

tON(MIN)fSW

where tON(MIN) is 100ns. The minimum input voltage is

limited by the maximum duty cycle (DMAX = 0.875):

VIN(MIN)

=

⎡ VOUT + VDROP1 ⎤

⎣⎢

0.875

⎦⎥

+

VDROP2 -

VDROP1

where VDROP1 is the sum of the parasitic voltage drops in

the inductor discharge path, including synchronous recti-

fier, inductor, and PCB resistances. VDROP2 is the sum of

the resistances in the charging path, including high-side

switch, inductor, and PCB resistances.

Setting the Switching Frequency

The controller generates the clock signal by dividing

down the internal oscillator or SYNC input signal when

driven by an external oscillator, so the switching

frequency equals half the oscillator frequency (fSW =

fOSC/2). The internal oscillator frequency is set by a

resistor (ROSC) connected from OSC to GND. The rela-

tionship between fSW and ROSC is:

6 × 109 Ω - Hz

ROSC =

S

fSW

where fSW is in Hz, fOSC is in Hz, and ROSC is in Ω. For

example, a 600kHz switching frequency is set with

ROSC = 10kΩ. Higher frequencies allow designs with

lower inductor values and less output capacitance.

Consequently, peak currents and I2R losses are lower

at higher switching frequencies, but core losses, gate-

charge currents, and switching losses increase.

A rising clock edge on SYNC is interpreted as a syn-

chronization input. If the SYNC signal is lost, the internal

oscillator takes control of the switching rate, returning

the switching frequency to that set by ROSC. This main-

tains output regulation even with intermittent SYNC sig-

nals. When an external synchronization signal is used,

ROSC should set the switching frequency to one half

SYNC rate (fSYNC).

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