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MAX9723AETE

Stereo DirectDrive Headphone Amplifier with BassMax, Volume Control, and I2C

Maxim Integrated 

MAX9723

Stereo DirectDrive Headphone Amplifier

with BassMax, Volume Control, and I2C

SDA

tLOW

tSU, DAT

tHD, DAT

SCL

tHD, STA

START

CONDITION

tHIGH

tR

tF

tSU, STA

tHD, STA

REPEATED

START

CONDITION

tBUF

tSP

tSU, STO

STOP

START

CONDITION CONDITION

Figure 3. 2-Wire Serial-Interface Timing Diagram

master, typically a microcontroller, generates SCL and

initiates data transfer on the bus.

A master device communicates to the MAX9723 by trans-

mitting the proper address followed by the data word.

Each transmit sequence is framed by a START (S) or

REPEATED START (Sr) condition and a STOP (P) condi-

tion. Each word transmitted over the bus is 8 bits long and

is always followed by an acknowledge clock pulse.

The MAX9723 SDA line operates as both an input and an

open-drain output. A pullup resistor, greater than 500Ω, is

required on the SDA bus. The MAX9723 SCL line oper-

ates as an input only. A pullup resistor, greater than 500Ω,

is required on SCL if there are multiple masters on the bus,

or if the master in a single-master system has an open-

drain SCL output. Series resistors in line with SDA and

SCL are optional. Series resistors protect the digital inputs

of the MAX9723 from high-voltage spikes on the bus lines,

and minimize crosstalk and undershoot of the bus signals.

Bit Transfer

One data bit is transferred during each SCL cycle. The

data on SDA must remain stable during the high period

of the SCL pulse. Changes in SDA while SCL is high are

control signals (see the START and STOP Conditions sec-

tion). SDA and SCL idle high when the I2C bus is not busy.

Start and Stop Conditions

SDA and SCL idle high when the bus is not in use. A mas-

ter device initiates communication by issuing a START

condition. A START condition is a high-to-low transition

on SDA with SCL high. A STOP condition is a low-to-high

transition on SDA while SCL is high (Figure 4). A START

condition from the master signals the beginning of trans-

mission to the MAX9723. The master terminates trans-

mission and frees the bus by issuing a STOP condition.

The bus remains active if a REPEATED START condition

is generated instead of a STOP condition.

Early STOP Conditions

The MAX9723 recognizes a STOP condition at any point

during data transmission except if the STOP condition

occurs in the same high pulse as a START condition.

Slave Address

The MAX9723 is available with one of two preset slave

addresses (see Table 1). The address is defined as the

seven most significant bits (MSBs) followed by the Read/

Write (R/W) bit. The address is the first byte of informa-

tion sent to the MAX9723 after the START condition. The

MAX9723 is a slave device only capable of being written

to. The sent R/W bit must always be a zero when config-

uring the MAX9723.

The MAX9723 acknowledges the receipt of its address

even if R/W is set to 1. However, the MAX9723 will not

drive SDA. Addressing the MAX9723 with R/W set to 1

causes the master to receive all 1’s regardless of the

contents of the command register.

Acknowledge

The acknowledge bit (ACK) is a clocked 9th bit that the

MAX9723 uses to handshake receipt of each byte of

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