MB88156-000 Просмотр технического описания (PDF) - Fujitsu

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производитель

MB88156-000

Spread Spectrum Clock Generator

Fujitsu 

MB88156

■ LOCK-UP TIME

3.0 V

VDD

External clock

stabilization wait time

XIN

XPD

VIH

SPRD,

VIH

MLTP0,

MLTP1,

FREQ, ENS,

SEL

CKOUT

tLK

(Lock-up time)

If the XPD pin is fixed at the “H” level, the maximum time after the power is turned on until the set clock signal is

output from CKOUT pin is (the stabilization wait time of input clock to XIN pin) + (the lock-up time “tLK”). For the

input clock stabilization time, check the characteristics of the resonator or oscillator used.

VDD

3.0 V

External clock

stabilization wait time

XIN

XPD

SPRD,

MLTP0,

VIH

MLTP1,

FREQ,

ENS,

SEL

CKOUT

VIH

tLK

(Lock-up time)

If the XPD pin is used for power-down control, the set clock signal is output from the CKOUT pin at most the lock-

up time “tLK” after the XPD pin goes “H” level.

(Continued)

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