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MC100E451FN

5V ECL 6−Bit D Register Differential Data and Clock

ON Semiconductor 

MC10E451, MC100E451

5V ECL 6−Bit D Register

Differential Data and Clock

Description

The MC10E/100E451 contains six D−type flip−flops with

single−ended outputs and differential data inputs. The common clock

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input is also differential. The registers are triggered by a positive

transition of the positive clock (CLK) input.

A HIGH on the Master Reset (MR) input resets all Q outputs to

LOW.

The differential input structures are clamped so that the inputs of

PLCC−28

FN SUFFIX

CASE 776

unused registers can be left open without upsetting the bias network of

the device. The clamping action will assert the D and the CLK sides of

the inputs. Because of the edge triggered flip−flop nature of the device

MARKING DIAGRAM*

simultaneously opening both the clock and data inputs will result in an

1 28

output which reaches an unidentified but valid state. Note that the

input clamps only operate when both inputs fall to 2.5 V below VCC.

The VBB pin, an internally generated voltage supply, is available to

this device only. For single−ended input conditions, the unused

differential input is connected to VBB as a switching reference voltage.

VBB may also rebias AC coupled inputs. When used, decouple VBB

and VCC via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, VBB should be left open.

The 100 Series contains temperature compensation.

MCxxxE451FNG

AWLYYWW

xxx

= 10 or 100

A

= Assembly Location

WL

= Wafer Lot

Features

• Differential Inputs: Data and Clock

• VBB Output

• 1100 MHz Min. Toggle Frequency

• Asynchronous Master Reset

YY

= Year

WW = Work Week

G

= Pb−Free Package

*For additional marking information, refer to

Application Note AND8002/D.

• PECL Mode Operating Range:

VCC = 4.2 V to 5.7 V with VEE = 0 V

• NECL Mode Operating Range:

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

VCC = 0 V with VEE = −4.2 V to −5.7 V

• Internal Input 50 kW Pulldown Resistors

• Moisture Sensitivity Level:

• ESD Protection: Human Body Model; > 2 kV,

Pb = 1;

Machine Model; > 200 V

• Transistor Count = 348 devices

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC

Latchup Test

• Flammability Rating: UL 94 V−0 @ 0.125 in,

Pb−Free = 3

For Additional Information, see Application Note

AND8003/D

• Pb−Free Packages are Available*

Oxygen Index: 28 to 34

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2006

1

November, 2006 − Rev. 9

Publication Order Number:

MC10E451/D

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