MC14541B
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD
Min
Typ
Max
(Note 6)
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
Propagation Delay, Clock to Q (28 Output)
tPLH, tPHL = (1.7 ns/pF) CL + 3415 ns
tPLH, tPHL = (0.66 ns/pF) CL + 1217 ns
tPLH, tPHL = (0.5 ns/pF) CL + 875 ns
Propagation Delay, Clock to Q (216 Output)
tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns
tPHL, tPLH = (0.66 ns/pF) CL + 3467 ns
tPHL, tPLH = (0.5 ns/pF) CL + 2475 ns
Clock Pulse Width
tTLH,
tTHL
5.0
−
100
200
10
−
50
100
15
−
40
80
tPLH
tPHL
5.0
−
3.5
10.5
10
−
1.25
3.8
15
−
0.9
2.9
tPHL
tPLH
5.0
−
6.0
18
10
−
3.5
10
15
−
2.5
7.5
tWH(cl)
5.0
900
300
−
10
300
100
−
15
225
85
−
Clock Pulse Frequency (50% Duty Cycle)
fcl
5.0
−
1.5
0.75
10
−
4.0
2.0
15
−
6.0
3.0
MR Pulse Width
tWH(R)
5.0
900
300
−
10
300
100
−
15
225
85
−
Master Reset Removal Time
trem
5.0
420
210
−
10
200
100
−
15
200
100
−
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Unit
ns
ms
ms
ns
MHz
ns
ns
VDD
VDD
PULSE
GENERATOR
RS
AR
Q/Q SELECT
MODE
Q
A
CL
B
MR
VSS
(Rtc AND Ctc OUTPUTS ARE LEFT OPEN)
20 ns
20 ns
90% 50%
10%
50%
DUTY CYCLE
Figure 1. Power Dissipation Test Circuit
and Waveform
PULSE
GENERATOR
RS
AR
Q/Q SELECT
MODE
Q
A
CL
B
MR
VSS
20 ns
RS
tPLH
90% 50%
10%
50% 90%
Q
10%
tTLH
20 ns
50%
50%
tPHL
tTHL
Figure 2. Switching Time Test Circuit
and Waveforms
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