MC14536B Просмотр технического описания (PDF) - Motorola => Freescale
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MC14536B Datasheet PDF : 13 Pages
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ÎÎÎÎSÎÎÎÎWIÎÎÎÎTCHÎÎÎÎINGÎÎÎÎCHÎÎÎÎARÎÎÎÎAChCaÎÎÎÎTrEacRtÎÎÎÎeISriTsÎÎÎÎtIiCcSÎÎÎÎ* (CÎÎÎÎL=5ÎÎÎÎ0pFÎÎÎÎ,TAÎÎÎÎ=2ÎÎÎÎ5_CÎÎÎÎ)SymÎÎÎÎbolÎÎÎÎÎÎÎÎVÎÎÎÎDDÎÎÎÎÎÎÎÎÎÎÎÎMinÎÎÎÎÎÎÎÎTÎÎÎÎypÎÎÎÎ# ÎÎÎÎÎÎÎÎMaxÎÎÎÎÎÎÎÎUÎÎÎÎnitÎÎÎÎ
Output Rise and Fall Time (Pin 13)
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
Propagation Delay Time
Clock to Q1, 8–Bypass (Pin 6) High
tPLH, tPHL = (1.7 ns/pF) CL + 1715 ns
tPLH, tPHL = (0.66 ns/pF) CL + 617 ns
tPLH, tPHL = (0.5 ns/pF) CL + 425 ns
tTLH,
ns
tTHL
5.0
—
100
200
10
—
50
100
15
—
40
80
tPLH,
ns
tPHL
5.0
—
1800
3600
10
—
650
1300
15
—
450
1000
Clock to Q1, 8–Bypass (Pin 6) Low
tPLH, tPHL = (1.7 ns/pF) CL + 3715 ns
tPLH, tPHL = (0.66 ns/pF) CL + 1467 ns
tPLH, tPHL = (0.5 ns/pF) CL + 1075 ns
Clock to Q16
tPHL, tPLH = (1.7 ns/pF) CL + 6915 ns
tPHL, tPLH = (0.66 ns/pF) CL + 2967 ns
tPHL, tPLH = (0.5 ns/pF) CL + 2175 ns
Reset to Qn
tPHL = (1.7 ns/pF) CL + 1415 ns
tPHL = (0.66 ns/pF) CL + 567 ns
tPHL = (0.5 ns/pF) CL + 425 ns
Clock Pulse Width
tPLH,
tPHL
tPLH,
tPHL
tPHL
tWH
µs
5.0
—
3.8
7.6
10
—
1.5
3.0
15
—
1.1
2.3
µs
5.0
—
7.0
14
10
—
3.0
6.0
15
—
2.2
4.5
ns
5.0
—
1500
3000
10
—
600
1200
15
—
450
900
5.0
600
300
10
200
100
15
170
85
—
ns
—
—
Clock Pulse Frequency
(50% Duty Cycle)
fcl
5.0
—
1.2
0.4
MHz
10
—
3.0
1.5
15
—
5.0
2.0
Clock Rise and Fall Time
tTLH,
5.0
tTHL
10
15
—
No Limit
Reset Pulse Width
tWH
5.0
1000
500
—
ns
10
400
200
—
15
300
150
—
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
PIN ASSIGNMENT
SET 1
RESET 2
IN 1 3
OUT 1 4
OUT 2 5
8–BYPASS 6
CLOCK INH 7
VSS 8
16 VDD
15 MONO IN
14 OSC INH
13 DECODE
12 D
11 C
10 B
9A
MOTOROLA CMOS LOGIC DATA
MC14536B
3
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