MC33996 Просмотр технического описания (PDF) - Freescale Semiconductor

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MC33996

16 Output Switch with SPI Control

Freescale Semiconductor 

LOGIC COMMANDS AND REGISTERS

INTRODUCTION

on output drain-to-source voltage (VDS ) > 2.7V. This feature

is designed to provide protection to loads that experience

more than expected currents and require fast shutdown. The

33996 is designed to operate in both modes with full device

protection.

PWM ENABLE REGISTER

The PWM Enable register determines the outputs that are

PWM controlled. The first 8 bits of the 24 bit SPI message

word are used to identify the PWM enable command, and the

remaining 16 bits are used to enable and disable the PWM of

the output drivers.

A logic [0] in the PWM Enable register will disable the

outputs as PWM. A logic [1] in the PWM Enable register will

set the specific output as a PWM. Power-ON Reset or the

RST pin or the RESET command will set the PWM Enable

register to logic [0].

AND/OR CONTROL REGISTER

The AND /OR Control register describes the condition by

which the PWM pin controls the output driver. A logic [0] in

the AND /OR Control register will AND the PWM input pin with

the ON /OFF Control register bit. Likewise, a logic [1] in the

AND /OR Control register will OR the PWM input pin with the

ON /OFF Control register bit (see Figure 12). For the AND /

OR control to occur, the PWM Enable bit must be set to

logic [1].

On/Off Control Bit

On/Off Control Bit

PWM Enable Bit

PWM IN

AND/OR Control Bit

To Gate

Control

On/Off control Bit

PWM IN

Figure 12. PWM Control Logic Diagram

SERIAL OUTPUT (SO) RESPONSE REGISTER

Fault reporting is accomplished through the SPI interface.

All logic [1s] received by the MCU via the SO pin indicate

fault. All logic [0s] received by the MCU via the SO pin

indicate no fault. All fault bits are cleared on the positive edge

of CS. SO bits 15 to 0 represent the fault status of outputs 15

to 0. SO bits 21 to 16 will always return logic [0]. Bit 22

provides over-voltage condition status and bit 23 is set when

any fault is present in the IC. The timing between two write

words must be greater than 450μs to allow adequate time to

sense and report the proper fault status.

RESET COMMAND

The RESET command turns all outputs OFF and sets the

following registers to a POR state (refer to Table 6).

• ON/OFF Control Register

• SFPD Control Register

• PWM Enable Register

• AND/OR Control Register

The Open Load Current Enable and the Global Shutdown

Registers are not affected by the RESET command.

33996

14

Analog Integrated Circuit Device Data

Freescale Semiconductor

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