MGA-71543-BLK Просмотр технического описания (PDF) - HP => Agilent Technologies
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MGA-71543-BLK Datasheet PDF : 24 Pages
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MGA-71543 Electrical Specifications
Tc = +25°C, Zo = 50Ω, Id = 10 mA, Vd = 3V, unless noted
Symbol
Parameter and Test Condition
Units Min. Typ.
Max. σ [1]
Vref test
NF test
Gain test
IIP3 test
Gain, Bypass
Vds = 2.4 V
f = 2.01 GHz Vd = 3.0 V (= Vds - Vref)
f = 2.01 GHz Vd = 3.0 V (= Vds - Vref)
f = 2.01 GHz Vd = 3.0 V (= Vds - Vref)
f = 2.01 GHz Vds = 0 V, Vref = -3V
Bypass Mode[6]
Id = 10 mA
Id = 10 mA
Id = 10 mA
Id = 10 mA
Id = 0 mA
V
-0.86
-0.65
-0.43
0.041
dB
1.1
1.45
0.02
dB
14.4
15.9
17.4
0.24
dBm
1
3.0
0.96
dB
-6.4
-5.6
0.12
Ig test
Bypass Mode Vds = 0 V, Vref = -3 V[6]
Id = 0 mA
µA
NFmin [3]
Minimum Noise Figure
f = 0.9 GHz
dB
As measured in Figure 5 Test Circuit
f = 1.5 GHz
(Γopt computed from s-parameter and
f = 1.9 GHz
noise parameter performance as measured f = 2.1 GHz
in a 50Ω impedance fixture)
f = 2.5 GHz
f = 6.0 GHz
2.0
1.5
0.7
0.7
0.8
0.8
0.8
1.1
Ga[3]
Associated Gain at Nfo
f = 0.9 GHz
dB
17.1
As measured in Figure 5 Test Circuit
f = 1.5 GHz
16.4
(Gopt computed from s-parameter and
f = 1.9 GHz
15.8
noise parameter performance as measured f = 2.1 GHz
15.4
in a 50Ω impedance fixture)
f = 2.5 GHz
14.9
f = 6.0 GHz
10.0
P1dB
IIP3
Switch
Output Power at 1 dB Gain Compression
Id = 6 mA
dBm
As measured in Evaluation Test Circuit with Id = 10 mA
source resistor biasing[4,5]
Id = 20 mA
Frequency = 2.01 GHz
Id = 40 mA
Input Third Order Intercept Point
I = 6 mA
dBm
d
As measured in Figure 4 Test Circuit[5]
I = 10 mA
d
Frequencies = 2.01 GHz, 2.02 GHz
Id = 20 mA
Id = 40 mA
Bypass Switch Rise/Fall Time
(10% - 90%)
Intrinsic
As measured in Evaluation Test Circuit
Eval Circuit
nS
+3.0
+7.4
+13.1
+15.5
-0.5
+3.0
+7.4
+8.7
10
100
RLin
Input Return Loss as measured in Fig. 4
f = 2.01 GHz
dB
6.0
0.31
RLout
Output Return Loss as measured in Fig. 4
f = 2.01 GHz
dB
10.9
0.65
ISOL
Isolation |s12|2 as measured in Fig. 5
f = 2.01 GHz
dB
-22.5
Notes:
1. Standard Deviation and Typical Data based at least 450 part sample size from 9 wafers. Future wafers allocated to this product may have nominal
values anywhere within the upper and lower spec limits.
2. Measurements made on a fixed tuned production test circuit (Figure 4) that represents a trade-off between optimal noise match, maximum gain
match, and a realizable match based on production test board requirements at 10 mA bias current. Excess circuit losses have been de-embedded
from actual measurements. Vd=Vds-Vref where Vds is adjusted to maintain a constant Vd bias equivalent to a single supply 3V bias application.
Consult Applications Note for circuit biasing options.
3. Minimum Noise Figure and Associated Gain data computed from s-parameter and noise parameter data measured in a 50Ω system using ATN NP5
test system. Data based on 10 typical parts from 9 wafers. Associated Gain is the gain when the product input is matched for minimum Noise Figure.
4. P1dB measurements were performed in the evaluation circuit with source resistance biasing. As P1dB is approached, the drain current is
maintained near the quiescent value by the feedback effect of the source resistor in the evaluation circuit. Consult Applications Note for circuit
biasing options.
5. Measurements made on a fixed tuned production test circuit that represents a trade-off between optimal noise match, maximum gain match, and a
realizable match based on production test board requirements at 10 mA bias current. Performance may be optimized for different bias conditions
and applications. Consult Applications Note.
6. The Bypass Mode test conditions are required only for the production test circuit (Figure 4) using the gate bias method. In the preferred source
resistor bias configuration, the Bypass Mode is engaged by presenting a DC open circuit instead of the bias resistor on Pin 4.
3
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