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MIC2164 Просмотр технического описания (PDF) - Micrel

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MIC2164 Datasheet PDF : 39 Pages
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Micrel, Inc.
Figure 5a. Enough Ripple at FB
Figure 5b. Inadequate Ripple at FB
Figure 5c. Invisible Ripple at FB
In this situation, the output voltage ripple is less than
20mV. Therefore, additional ripple is injected into the FB
pin from the switching node LX via a resistor Rinj and a
capacitor Cinj, as shown in Figure 5c. The injected ripple
is:
1
ΔVFB(pp)
=
VHSD ×K div
×D×(1- D)×
fSW
×τ
(29)
K div
=
R1//R2
Rinj + R1//R2
(30)
where
VHSD = Power stage input voltage at HSD pin
D = Duty Cycle
fSW = switching frequency
τ = (R1// R2 // Rinj) Cff
MIC2164/-2/-3/C
In the formula (29) and (30), it is assumed that the time
constant associated with Cff must be much greater than
the switching period:
1T
= << 1
fsw × τ τ
If the voltage divider resistors R1 and R2 are in the k
range, a Cff of 1nF to 100nF can easily satisfy the large
time constant consumption. Also, a 100nF injection
capacitor Cinj is used in order to be considered as short
for a wide range of the frequencies.
The process of sizing the ripple injection resistor and
capacitors is:
Step 1. Select Cff to feed all output ripples into the
feedback pin and make sure the large time constant
assumption is satisfied. Typical choice of Cff is 1nF to
100nF if R1 and R2 are in krange.
Step 2. Select Rinj according to the expected feedback
voltage ripple. According to the equation (30):
K div
=
ΔVFB(pp)
VHSD
fSW ⋅ τ
D (1D)
(31)
Then the value of Rinj is obtained as:
R inj
= (R1// R2) ( 1
K div
1)
(32)
Step 3. Select Cinj as 100nF, which could be considered
as short for a wide range of the frequencies.
September 2010
20
M9999-091310-D

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