MM74HC00 Просмотр технического описания (PDF) - Fairchild Semiconductor
Номер в каталоге
Компоненты Описание
производитель
MM74HC00 Datasheet PDF : 7 Pages
| |||
September 1983
Revised January 2005
MM74HC00
Quad 2-Input NAND Gate
General Description
The MM74HC00 NAND gates utilize advanced silicon-gate
CMOS technology to achieve operating speeds similar to
LS-TTL gates with the low power consumption of standard
CMOS integrated circuits. All gates have buffered outputs.
All devices have high noise immunity and the ability to
drive 10 LS-TTL loads. The 74HC logic family is function-
ally as well as pin-out compatible with the standard 74LS
logic family. All inputs are protected from damage due to
static discharge by internal diode clamps to VCC and
ground.
Features
s Typical propagation delay: 8 ns
s Wide power supply range: 2–6V
s Low quiescent current: 20 µA maximum (74HC Series)
s Low input current: 1 µA maximum
s Fanout of 10 LS-TTL loads
Ordering Code:
Order Number
Package
Number
Package Description
MM74HC00M
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC00MX_NL
M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC00SJ
M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC00MTC
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC00MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
MM74HC00N
N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74HC00N_NL
N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Logic Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
© 2005 Fairchild Semiconductor Corporation DS005292
www.fairchildsemi.com
Share Link: 