GLT4160L04-50J3 Просмотр технического описания (PDF) - G-Link Technology

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GLT4160L04-50J3

4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

G-Link Technology  

G-LINK

GLT4160L04

4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

Nov 2001 (Rev.3.2)

Notes:

1. Measure with a load equivalent to one TTL input and 100 pF.

2. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), access time will be tAA

dominant.

3. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRAD (max.), access time will be

controlled by tCAC.

4. Either tRRH or tRCH must be satisfied for a Read Cycle.

5. Access time is determined by the longest of tAA, tCAC and tCPA.

6. Assumes that tRAD ≥ tRAD (max.).

7. Assumes that tRCD ≥ tRCD (max.).

8. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.

9. tWCS (min.) must be satisfied in an Early Write Cycle.

10. tDS and tDH are referenced to the latter occurrence of CAS or WE .

11. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 2 ns.

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