¡ Semiconductor
MSM7660
Horizontal Valid Timer
Position adjustment of horizontal valid pixel timing signal
HVALT [7:4]
:Adjusting the starting position
Register Setting Value (Ox) 8 9 A B C D E F 0 1 2 3 4 5 6 7
Adjusted Value (Pixel) –8 –7 –6 –5 –4 –3 –2 –1 0 +1 +2 +3 +4 +5 +6 +7
HVALT [3:0]
:Adjusting the end position
Register Setting Value (Ox) 8 9 A B C D E F 0 1 2 3 4 5 6 7
Adjusted Value (Pixel) –8 –7 –6 –5 –4 –3 –2 –1 0 +1 +2 +3 +4 +5 +6 +7
Vertical Valid Timer
Position adjustment of vertical valid line timing signal
VVALT [7:4]
:Adjusting the starting position
Register Setting Value (Ox) 8 9 A B C D E F 0 1 2 3 4 5 6 7
Adjusted Value (Line) –8 –7 –6 –5 –4 –3 –2 –1 0 +1 +2 +3 +4 +5 +6 +7
VVALT [3:0]
:Adjusting the end position
Register Setting Value (Ox) 8 9 A B C D E F 0 1 2 3 4 5 6 7
Adjusted Value (Line) –8 –7 –6 –5 –4 –3 –2 –1 0 +1 +2 +3 +4 +5 +6 +7
AGC Loop filter control
AGCLF [5:0]
:Adjusting sync level
Register Setting
MSB [5 : 4]
Value
(Ox)
2301
0 –32 –16 0 +16
1 –31 –15 +1 +17
2 –30 –14 +2 +18
3 –29 –13 +3 +19
4 –28 –12 +4 +20
5 –27 –11 +5 +21
6 –26 –10 +6 +22
LSB 7 –25 –9 +7 +23
[3 : 0] 8 –24 –8 +8 +24
9 –23 –7 +9 +25
A –22 –6 +10 +26
B –21 –5 +11 +27
C –20 –4 +12 +28
D –19 –3 +13 +29
E –18 –2 +14 +30
F –17 –1 +15 +31
29/35