NCP362(2009) Просмотр технического описания (PDF) - ON Semiconductor
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Компоненты Описание
производитель
NCP362
(Rev.:2009)
(Rev.:2009)
ON Semiconductor
NCP362 Datasheet PDF : 16 Pages
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NCP362
IEC 61000−4−2 Spec.
Level
Test
Voltage
(kV)
First Peak
Current Current at
(A)
30 ns (A)
1
2
7.5
4
2
4
15
8
3
6
22.5
12
4
8
30
16
Current at
60 ns (A)
2
4
6
8
IEC61000−4−2 Waveform
Ipeak
100%
90%
I @ 30 ns
I @ 60 ns
10%
Figure 26. IEC61000−4−2 Spec
tP = 0.7 ns to 1 ns
ESD Gun
TVS
Oscilloscope
50 W
Cable
50 W
Figure 27. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping
voltage at the device level. ON Semiconductor has
developed a way to examine the entire voltage waveform
across the ESD protection diode over the time domain of
an ESD pulse in the form of an oscilloscope screenshot,
which can be found on the datasheets for all ESD protection
diodes. For more information on how ON Semiconductor
creates these screenshots and how to interpret them please
refer to AND8307/D.
100
tr
90
80
70
60
50
PEAK VALUE IRSM @ 8 ms
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
HALF VALUE IRSM/2 @ 20 ms
40
30
tP
20
10
0
0
20
40
60
80
t, TIME (ms)
Figure 28. 8 X 20 ms Pulse Waveform
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