NJU8754 Просмотр технического описания (PDF) - Japan Radio Corporation

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NJU8754

Analog Signal Input Monaural Class D Power Amplifier

Japan Radio Corporation  

NJU8754

BLOCK DIAGRAM

VDD

VSS

IN

COM

-

+

-

+

Soft Start

Control Logic

MUTE STBY

Pulse

Width

Modulator

Short

Protection

Low BATT

Protection

OUTP

VDDO

OUTN

PIN DESCRIPTION

No.

SSOP10

QFN20

SYMBOL I/O

FUNCTION

1

19

VDD

− Power supply : VDD=3.6V

2

2

IN

I Signal input

3

3

COM

− Analog common

4

4

MUTE

I

Mute control

Low : Mute ON High : Mute OFF

5

7

STBY

I

Standby control

Low : Standby ON High : Standby OFF

6

9,10

VSS

− Power GND : VSS=0V

7

12

OUTN

O Negative output

8

13

VDDO

− Output power supply

9

14

OUTP

O Positive output

10

16,17

VSS

− Power GND : VSS=0V

−

1,5,6,8,11,15,18,20

NC

− Non connection

*The relations of ”VSS= 0V” and “VDD= VDDO” must be maintained.

*VSS(SSOP10:Pin No.6,10, QFN20:Pin No.9,10,16,17) should be connected at a nearest point to the IC.

*VDDO(SSOP10:Pin No.8, QFN20:Pin No.13) should be connected at a nearest point to the IC.

*MUTE(SSOP10, QFN20:Pin No.4) and STBY(SSOP10:Pin No.5, QFN20:Pin No.7) must be connected

to VDD, when these pins are not used.

-2-

Ver.2003-03-12

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