ADV7202 Просмотр технического описания (PDF) - Analog Devices
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ADV7202 Datasheet PDF : 28 Pages
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ADV7202
3.3 V SPECIFICATIONS (AVDD/DVDD = 3.3 V ؎ 5%, VREF = 1.235 V, RSET = 1.2 k⍀, all specifications TMIN to TMAX1, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions
STATIC PERFORMANCE_DAC
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
VIDEO ADC
Resolution
Accuracy
Integral Nonlinearity
Differential Nonlinearity
Differential Input Voltage Range2
SNR
AUX ADC
Resolution
Differential Nonlinearity
Integral Nonlinearity
Input Voltage Range
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Output Capacitance
Digital Output Access Time, t14
Digital Output Hold Time, t15
ANALOG OUTPUTS
Output Current
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Analog Output Delay3
DAC Output Skew
10
Bits
10
Bits
±1
LSB
–0.8/0.1
LSB
12
12
±4
±1
–VREFADC
60
55
Bits
+VREFADC
Bits
LSB
LSB
dB
dB
8
Bits
± 0.5
LSB
± 0.5
LSB
0
2 VREFADC V
2
V
0.8
V
±1
µA
10
pF
2.4
V
0.4
V
10
µA
10
pF
6
ns
5
ns
4.33
mA
4
%
0
1.4
V
50
kΩ
30
pF
5.5
ns
0.06
ns
10-Bit Operation
10-Bit Operation
(Including 2 Bits for Gain Ranging)
2.2 V Ref.
12 Bit
12 Bit
See Table II
27 MHz Clock, fIN = 100 kHz
54 MHz Clock
ISOURCE = 400 µA
ISINK = 1.6 mA
See Figure 13
RSET = 1.2 kΩ, RL = 300 Ω
DAC 0, 1, and 2
IOUT = 0 mA
VOLTAGE REFERENCE
Reference Range, VREFADC
Reference Range, VREFDAC
1.100
V
1.235
V
NOTES
10°C to 70°C.
2SHA gain = 1, half range for SHA gain = 2, see Table II.
3Output delay measured from 50% of the rising edge of the clock to the 50% point of full-scale transition.
Specifications subject to change without notice.
REV. 0
–5–
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