CXD2302Q Просмотр технического описания (PDF) - Sony Semiconductor

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CXD2302Q

8-bit 50MSPS Video A/D Converter with Clamp Function

Sony Semiconductor 

CXD2302Q

2. This IC uses an offset cancel type comparator which operates synchronously with an external clock. It

features the following operating modes which are respectively indicated on the timing chart II with S, H, C

symbols. That is input sampling (auto zero) mode, input hold mode and comparison mode.

3. The operation of respective parts is as indicated in the Timing Chart II. For instance input voltage Vi (1) is

sampled with the falling edge of the external clock (1) by means of the upper comparator block and the

lower comparator A block.

The upper comparator block finalizes comparison data MD (1) with the rising edge of the external clock (2).

Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to

the upper results. The lower comparator A block finalizes comparison data LD (1) with the rising edge of

the external clock (3). MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the

external clock (4). Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital

data output.

Operation Notes

1. VDD, VSS

To reduce noise effects, separate the analog and digital systems close to the device. For both the digital

and analog VDD pins, use a ceramic capacitor of about 0.1µF set as close as possible to the pin to bypass

to the respective GND’s.

2. Analog input

Compared with the flash type A/D converter, the input capacitance of the analog input is rather small.

However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability.

When driving with an amplifier of low output impedance, parasitic oscillation may occur. That may be

prevented by insetting a resistance of about 33Ω in series between the amplifier output and A/D input.

When the VIN signal of pin No. 21 is monitored, the kickback noise of clock is. However, this has no effect

on the characteristics of A/D conversion.

3. Clock input

The clock line wiring should be as short as possible also, to avoid any interference with other signals,

separate it from other circuits.

4. Reference input

Voltage VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and VRB pins

to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained. By shorting VDD and

VRTS, VSS and VRBS respectively, the self-bias function that generates VRT=about 2.5V and VRB=about

0.6V, is activated.

5. Timing

Analog input is sampled with the falling edge of CLK and output as digital data synchronized with a delay

of 2.5 clocks and with the following rising edge. The delay from the clock rising edge to the data output is

about 9ns (DVDD = 5V).

6. OE pin

Pins 1 to 8 (D0 to D7) are in the output mode by leaving OE open or connecting it to DVSS, and they are in

the high impedance mode by connecting it to DVDD.

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