UPC659AGS Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPC659AGS

8-BIT A/D CONVERTER FOR VIDEO PROCESSING WITH REFERENCE GENERATOR AND CLAMP CIRCUIT

NEC => Renesas Technology 

µPC659A

ATTENTION FOR APPLICATION

• Converted data output

Analog signal is captured at the rising edge, and converted data will be output at the rising edge after 1 clock pulse.

For the µPC659, 2 clock pulses.

• Analog input terminal

In case the pedestal level is clamped, the clamp circuit uses the soft clamp circuit to protect the burst level. However,

if a high impedance output is connected to the VIN pin (pin 4), the burst level will be reduced (for example, for an

external impedance of 10 Ω, the burst level is reduced by approx. 3 %).

Therefore, connect the lowest possible impedance signal to the analog signal input pin.

Low output

impedance

buffer

VIN

4

Clamp pulse

6

PCL

7

Clamp voltage

VCL

AGND

µPC659A

• If don’s use the clamp circuit

PCL pin (pin 6) and GND must be short-circuit. And insert by-pass capacitor of about 0.1 µF between the VCL pin

(pin 7) and GND. Input analog signal to VIN pin (pin 4).

In case an external clamp circuit is used, connect the PCL pin (pin 6) to GND, and leave the VCL pin (pin 7)

unconnected. Set the voltage of the VIN pin (pin 4) between 2.3 V and 3.3 V.

• Clamp voltage

There is a few difference clamp voltage between the supply clamp voltage VCL (pin 7) and really clamp voltage.

Really clamp voltage = VCL + α

Take account of the α (about ±20 mV) at supply VCL to pin 7.

• When reference voltage is set from external, VRB (pin 10) = 2.3 V, VRT (pin 1) = 3.3 V .

• Circuit current

Analog circuit current

Digital circuit current

Sum

TYP. (Unit: mA)

37

6

43

• Set the sampling clock frequency between 1 MHz and 20 MHz. If a frequency outside this range is used, the internal

sample-and-hold circuit will not function properly.

• First apply 5 V to the AVCC pins (pins 3 and 11) and the DVCC pin (pin 18), then input the analog signal to the VIN

pin (pin 4). If the analog signal is input first, the output data may latch up.

11

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