PCA9545APW118 Просмотр технического описания (PDF) - NXP Semiconductors.
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PCA9545APW118 Datasheet PDF : 32 Pages
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NXP Semiconductors
PCA9545A/45B/45C
4-channel I2C-bus switch with interrupt logic and reset
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master sends a
byte to the PCA9545A/45B/45C, which is stored in the control register. If multiple bytes
are received by the PCA9545A/45B/45C, it saves the last byte received. This register can
be written and read via the I2C-bus.
interrupt bits
(read only)
channel selection bits
(read/write)
76543210
INT INT
32
INT INT
10
B3
B2
B1
B0
channel 0
channel 1
channel 2
channel 3
INT0
INT1
INT2
INT3
002aab170
Fig 8. Control register
6.2.1 Control register definition
One or several SCx/SDx downstream pair, or channel, is selected by the contents of the
control register. This register is written after the PCA9545A/45B/45C has been addressed.
The 4 LSBs of the control byte are used to determine which channel is to be selected.
When a channel is selected, the channel will become active after a STOP condition has
been placed on the I2C-bus. This ensures that all SCx/SDx lines are in a HIGH state when
the channel is made active, so that no false conditions are generated at the time of
connection.
Table 4. Control register: write (channel selection); read (channel status)
INT3 INT2 INT1 INT0 B3 B2 B1 B0 Command
0
channel 0 disabled
X
X
X
X
X
X
X
1
channel 0 enabled
0
channel 1 disabled
X
X
X
X
X
X
X
1
channel 1 enabled
0
channel 2 disabled
X
X
X
X
X
X
X
1
channel 2 enabled
0
channel 3 disabled
X
X
X
X
X
X
X
1
channel 3 enabled
0
0
0
0
0
0
0
0
no channel selected;
power-up/reset default state
Remark: Several channels can be enabled at the same time. Example: B3 = 0, B2 = 1,
B1 = 1, B0 = 0, means that channel 0 and channel 3 are disabled and channel 1 and
channel 2 are enabled. Care should be taken not to exceed the maximum bus capacity.
PCA9545A_45B_45C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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