IW4021BN Просмотр технического описания (PDF) - Integral Corp.
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IW4021BN Datasheet PDF : 4 Pages
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TECHNICAL DATA
IW4021B
8-Bit Shift Register
High-Voltage Silicon-Gate CMOS
The IW4021B is an Edge-Triggered 8-Bit Shift Register (Parallel-
to-Serial Converter) with a synchronous Serial Data Input (DS), a
Clock Input (CP), an asynchronous active HIGH Parallel Load Input
(PL), eight asynchronous Parallel Data Inputs (P0-P7) and Buffered
Parallel Outputs from the last three stages (Q5-Q7).
Information on the Parallel Data Inputs (P0-P7) is asynchronously
loaded into the register while the Parallel Load Input (PL) is HIGH,
independent of the Clock (CP) and Serial Data (DS) inputs. Data
present in the register is stored on the HIGH-to-LOW transition of the
Parallel Load Input (PL).
When the Parallel Load Input is LOW, data on the Serial Data
Input (DS) is shifted into the first register position and all the data in
the register is shifted one position to the right on the LOW-to-HIGH
transition of the Clock Input (CP).
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
IW4021BN Plastic
IW4021BDW SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
FUNCTION TABLE
SERIAL OPERATION:
t CP DS PL
n
00
n+1
10
n+2
00
n+3
10
X0
Q5
t=n+6
0
1
0
1
Q5
Q6
t=n+7
0
1
0
Q6
Q7
t=n+8
0
1
Q7
PARALLEL OPERATION:
CP DS PL P5 P6 P7 Q5 Q6 Q7
X X 1 DDDDDD
X = don’t care
D = 1 or 0
1
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