PLL103-06 Просмотр технического описания (PDF) - PhaseLink Corporation

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PLL103-06

DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS

PhaseLink Corporation 

Preliminary PLL103-06

DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS

2. BYTE 7: Outputs Register (1=Enable, 0=Disable)

Bit

Pin#

Default Description

Bit 7

-

1

Reserved

Bit 6

19, 18

1

DDR3T_SDRAM6, DDR3C_SDRAM7

Bit 5

12, 13

1

DDR2T_SDRAM4, DDR2C_SDRAM5

Bit 4

-

Bit 3

-

1

Reserved

1

Reserved

Bit 2

7, 8

1

DDR1T_SDRAM2, DDR1C_SDRAM3

Bit 1

-

1

Reserved

Bit 0

3, 4

1

DDR0T_SDRAM0, DDR0C_SDRAM1

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 12/20/00 Page 4

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