S29AL016J70BFN020 Просмотр технического описания (PDF) - Spansion Inc.

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S29AL016J70BFN020

16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory

Spansion Inc. 

Data Sheet

Addresses

(Word Mode)

4Fh

50h

Table 9.4 Primary Vendor-Specific Extended Query (Sheet 2 of 2)

Addresses

(Byte Mode)

9Eh

A0h

Data

00XXh

00XXh

Description

WP# Protection

00 = Uniform Device without WP Protect

01 = Boot Device with TOP and Bottom WP Protect

02 = Bottom Boot Device with WP Protect

03 = Top Boot Device with WP Protect

04 = Uniform Device with Bottom WP Protect

05 = Uniform Device with Top WP Protect

06 = Uniform Device with All Sectors WP Protect

Program Suspend

00 = Not Supported, 01 = Supported

9.1 Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing provides data protection

against inadvertent writes (refer to Table 10.1 on page 35 for command definitions). In addition, the following

hardware data protection measures prevent accidental erasure or programming, which might otherwise be

caused by spurious system level signals during VCC power-up and power-down transitions, or from system

noise.

9.1.1

9.1.2

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC

power-up and power-down. The command register and all internal program/erase circuits are disabled, and

the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the

proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.

Write Pulse Glitch Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

9.1.3

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a logical one.

9.1.4

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising

edge of WE#. The internal state machine is automatically reset to reading array data on power-up.

February 18, 2010 S29AL016J_00_10

S29AL016J

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