SAA7158WP Просмотр технического описания (PDF) - Philips Electronics

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производитель

SAA7158WP

Back END IC

Philips Electronics 

Philips Semiconductors

Back END IC

Preliminary specification

SAA7158

PINNING

SYMBOL

TEST1/AP

Y0-0

Y0-1

Y0-2

Y0-3

Y0-4

Y0-5

VDD1

VSS1

Y0-6

Y0-7

UV0-0

UV0-1

UV0-2

UV0-3

TEST2/SP

RE2_OUT

RE1_OUT

RSTR

RE2_IN

RE1_IN

BLN

µPCL

µPDA

VSS2

CLK

VDD2

V1-0/Y2-0

V1-1/Y2-1

V1-2/Y2-2

V1-3/Y2-3

V1-4/Y2-4

V1-5/Y2-5

V1-6/Y2-6

V1-7/Y2-7

U1-0/UV2-0

U1-1/UV2-1

U1-2/UV2-2

U1-3/UV2-3

VSS3

July 1994

PIN

TYPE

1

input

2

3-state output

3

3-state output

4

3-state output

5

3-state output

6

3-state output

7

3-state output

8

supply

9

ground

10 3-state output

11 3-state output

12 3-state output

13 3-state output

14 3-state output

15 3-state output

16 input

17 output

18 output

19 input

20 input

21 input

22 input

23 input

24 in/output

25 ground

26 input

27 supply

28 input

29 input

30 input

31 input

32 input

33 input

34 input

35 input

36 input

37 input

38 input

39 input

40 ground

DESCRIPTION

action pin for testing; to be connected to VSS

feedback_data to second memory, Y bit 0

feedback_data to second memory, Y bit 1

feedback_data to second memory, Y bit 2

feedback_data to second memory, Y bit 3

feedback_data to second memory, Y bit 4

feedback_data to second memory, Y bit 5

positive digital supply voltage (+5 V)

digital ground

feedback_data to second memory, Y bit 6

feedback_data to second memory, Y bit 7

feedback_data to second memory, UV bit 0

feedback_data to second memory, UV bit 1

feedback_data to second memory, UV bit 2

feedback_data to second memory, UV bit 3

shift pin for testing; to be connected to VSS

redirected read enable to memory 2

redirected read enable to memory 1

memory read, µP interface and movie detection reset

input for read enable to memory 2

input for read enable to memory 1

blanking signal

clock for interface with 8051 UART, mode 0

data for interface with 8051 UART, mode 0

digital ground

master clock, nominal 27 (32) MHz

positive digital supply voltage (+5 V)

V data, bit 0 in 4:4:4; Y data second memory, bit 0

V data, bit 1 in 4:4:4; Y data second memory, bit 1

V data, bit 2 in 4:4:4; Y data second memory, bit 2

V data, bit 3 in 4:4:4; Y data second memory, bit 3

V data, bit 4 in 4:4:4; Y data second memory, bit 4

V data, bit 5 in 4:4:4; Y data second memory, bit 5

V data, bit 6 in 4:4:4; Y data second memory, bit 6

V data, bit 7 in 4:4:4; Y data second memory, bit 7

U data, bit 0 in 4:4:4; UV data second memory, bit 0

U data, bit 1 in 4:4:4; UV data second memory, bit 1

U data, bit 2 in 4:4:4; UV data second memory, bit 2

U data, bit 3 in 4:4:4; UV data second memory, bit 3

digital ground

4

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