SAF7115HW Просмотр технического описания (PDF) - NXP Semiconductors.
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SAF7115HW
NXP Semiconductors.
SAF7115HW Datasheet PDF : 35 Pages
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NXP Semiconductors
SAF7115
Multistandard video decoder
Table 4. Pin description …continued
Symbol
Pin
HTQFP100 TFBGA160
Real time signals
RTCO
36
P6
RTS1
35
N6
RTS0
34
P5
Clocks
LLC
28
P2
LLC2
29
N3
XTALI
7
D1
XTALO
6
C1
XTOUT
4
B1
Boundary scan test
TCK
98
B3
TDI
3
C2
TDO
2
B2
TMS
99
A2
TRST_N 97
A3
Test interface
TEST9
-
L11
TEST8
-
L10
TEST7
-
L5
TEST6
-
L4
TEST5
79
B12
TEST4
78
A13
TEST3
77
B14
TEST2
74
B13
TEST1
73
C14
TEST0
44
P10
Image port (I-port)
ICLK
45
N11
IDQ
46
P11
IGP1
49
N13
Type[1]
Description
(I/) O/st/pd real time control output[6]
O
real time status or sync information, controlled by subaddresses
11h and 12h
O
real time status or sync information, controlled by subaddresses
11h and 12h
O
line-locked system clock output (27 MHz nominal), for backward
compatibility; use pin XCLK for new applications
O
line locked 1/2 clock output (13.5 MHz nominal) for backward
compatibility; do not use for new applications
I
input terminal for 24.576 MHz (32.11 MHz) crystal oscillator or
connection of external oscillator with TTL compatible square wave
clock signal
O
24.576 MHz (32.11 MHz) crystal oscillator output; not connected
if pin XTALI is driven by an external single-ended oscillator
O
crystal oscillator output signal, auxiliary signal
I/pu
test clock for boundary scan test (with internal pull-up)[7]
I/pu
test data input for boundary scan test (with internal pull-up)[7]
O
test data output for boundary scan test[7]
I/pu
test mode select for boundary scan test or scan test (with internal
pull-up)[8]
I/pu
test reset for boundary scan test (active LOW with internal
pull-up); for board design without boundary scan connect
TRST_N to ‘ground’, e.g. through VSSD(CORE) or VSSD(IO)[8]
I/pd
do not connect, reserved for future extensions and for testing
AI
do not connect, reserved for future extensions and for testing
AI
do not connect, reserved for future extensions and for testing
I/pu
do not connect, reserved for future extensions and for testing
I/pu
do not connect, reserved for future extensions and for testing
O
do not connect, reserved for future extensions and for testing
I/pu
do not connect, reserved for future extensions and for testing
I/pu
do not connect, reserved for future extensions and for testing
I/pu
do not connect, reserved for future extensions and for testing
O
do not connect, reserved for future extensions and for testing
I/O
clock output signal for image port or optional asynchronous back
end clock input
O
output data qualifier for image port (optional: gated clock output)
O
general purpose output signal 1; image port (controlled by
subaddresses 84h and 85h); same functions as pin IGP0
SAF7115_1
Product data sheet
Rev. 01 — 15 October 2008
© NXP B.V. 2008. All rights reserved.
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