SC1116 Просмотр технического описания (PDF) - Semtech Corporation

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SC1116

Linear FET Controller For DDR Supplies

Semtech Corporation 

SC1116

POWER MANAGEMENT

Application Information

Overview

The SC1116 linear controller is designed to meet the

JEDEC specifications for termination of DDR-SDRAM.

Double Data Rate (DDR) memory is clocked at the same

speed as older SDRAM (synchronous dynamic random

access memory), yet handles twice the amount of data

by using the rising and falling edge of the clock signal for

data transfers. Another difference is that DDR memory

requires 2.5V instead of 3.3V used by standard SDRAM.

The other feature that separates DDR memory from a

conventional type is employment of the VTT – termination

voltage. Main requirements for the VTT are that it must

track variations of VDDQ and be able to supply (source)

current, and absorb (sink) current.

The SC1116 controller offers a low cost solution for DDR

termination voltage regulation by using external pass el-

ements (MOSFETs). Having the flexibility of choosing the

MOSFETs allows for optimization on the basis of cost/

size/performance of the specific application.

Test Circuit & Waveforms

The test circuit is shown below in Figure 1.

Note that VREF voltage is supplied externally to eliminate

inaccuracy caused by resistor divider.

V DDQ=2.5V

V cc=5V

V ref=1.25V

C1

1 00 uF

3 2m

Q1

IR37 14

U1

S C1 1 16

1 VCC

C2

1 uF

2 GND

DRVH 6

FB 5

3 R EF

DRVL 4

C3

0 .1uF

R3

1k

C4

4 .7n F

V TT =1.25V typ

+/-3A

Iso urce/ Isink 3A IsIosuinrcke

C6

2 70 uF

2 2m

0A to 6A 2SxteIspin k

Pu lse loa d, dc=50%

Po wer

Su pply

Q2

IR37 14

R4

1k

C5

4 .7nF

Cu rrent

Pro be

E lectronic

Loa d

Figure 1.

 2007 Semtech Corp.

4

www.semtech.com

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