SC174 Просмотр технического описания (PDF) - Semtech Corporation

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SC174

4A EcoSpeed™ Synchronous Step-Down Regulator with Optional Ultrasonic Power Save

Semtech Corporation 

SC174

Applications Information (continued)

ILPK

=

4A

+

1

2

× 0.511A=

4.26A

Rate of change of load current is

dI LOAD = 0.6A

dt

1m s

IMAX = maximum load release = 4A

L × ILPK - IMAX × dt

COUT = ILPK ×

VOUT dILOAD

2 × (VPK - VOUT )

2mH × 4.26A - 4A ×1ms

COUT = 4.26A ×

1V 0.6A

2 × (1.05V - 1V)

COUT = 79mF

Note that COUT is much smaller in this example, 79µF com-

pared to 353µF based upon a worst-case load release. To

meet the two design criteria of minimum 79µF and maxi-

mum 15mΩ ESR, select two capacitors rated at 47µF and

15mΩ ESR or less.

It is recommended that an additional small capacitor be

placed in parallel with COUT in order to filter high frequen-

cy switching noise.

Stability Considerations

Unstable operation is possible with adaptive on-time

controllers, and usually takes the form of double-pulsing

or ESR loop instability.

Double-pulsing occurs due to switching noise seen at

the FB input or because the FB ripple voltage is too low.

This causes the FB comparator to trigger prematurely af-

ter the minimum off-time has expired. In extreme cases

the noise can cause three or more successive on-times.

Double-pulsing will result in higher ripple voltage at the

output, but in most applications it will not affect opera-

tion. This form of instability can usually be avoided by

providing the FB pin with a smooth, clean ripple signal

that is at least 10mVp-p, which may dictate the need to

© 2010 Semtech Corporation

increase the ESR of the output capacitors. It is also im-

perative to provide a proper PCB layout as discussed in

the Layout Guidelines section.

Another way to eliminate doubling-pulsing is to add a

small (~ 10pF) capacitor across the upper feedback resis-

tor, as shown in Figure 8. This capacitor should be left

unpopulated unless it can be confirmed that double-

pulsing exists. Adding the CTOP capacitor will couple

more ripple into FB to help eliminate the problem. An

optional connection on the PCB should be available for

this capacitor.

CTOP

VOUT

R1

To FB pin

R2

Figure 8 — Capacitor Coupling to FB Pin

ESR loop instability is caused by insufficient ESR. The

details of this stability issue are discussed in the ESR Re-

quirements section. The best method for checking sta-

bility is to apply a zero-to-full load transient and observe

the output voltage ripple envelope for overshoot and

ringing. Ringing for more than one cycle after the initial

step is an indication that the ESR should be increased.

One simple way to solve this problem is to add trace re-

sistance in the high current output path. A side effect of

adding trace resistance is a decrease in load regulation.

ESR Requirements

A minimum ESR is required for two reasons. One reason

is to generate enough output ripple voltage to provide

10mVp-p at the FB pin (after the resistor divider) to avoid

double-pulsing.

The second reason is to prevent instability due to insuf-

ficient ESR. The on-time control regulates the valley of

the output ripple voltage. This ripple voltage is the sum

of the two voltages. One is the ripple generated by the

ESR, the other is the ripple due to capacitive charging

17

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