SD1010D Просмотр технического описания (PDF) - Unspecified
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SD1010D Datasheet PDF : 40 Pages
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synchronization pulse width and valid data window. The timing information is used to generate
the frequency divider for the output PLL, to lock the PLL output clock with HSYNC for the
LCD data clock, and to synchronize the output VSYNC and input VSYNC.
EEPROM interface
As mentioned in previous sections, the external EEPROM stores crucial information for the
SD1010D internal operations. The SD1010D interfaces with the EEPROM through a 2-wire
serial interface. The suggested EEPROM device is an industry standard serial-interface
EEPROM (24x08). The 2-wire serial interface scheme is briefly described here and a detailed
description can be found in public literature.
xi)
2-wire serial interface
The 2-wire serial interface uses 2 wires, SCL and SDA. The SCL is driven by the SD1010D and
used mainly as the sampling clock. The SDA is a bi-directional signal and used mainly as a data
signal. Figure 4 shows the basic bit definitions of the 2-wire serial interface.
The 2-wire serial interface supports random and sequential read operations. Figures 5 and 6
show the data sequences for random read and sequential read operations.
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