MID400(2003) Просмотр технического описания (PDF) - Fairchild Semiconductor
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MID400 Datasheet PDF : 11 Pages
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AC LINE MONITOR
LOGIC-OUT DEVICE
MID400
ISOLATION CHARACTERISTICS (TA = 25°C)
Characteristics
Test Conditions Symbol Min
Typ
Max Units
Steady State Isolation Voltage
Isolation Resistance
Isolation Capacitance
Relative Humidity ≤ 50%, II-O ≤ 10 µA,
1 Minute, 60 Hz
(VI-O = 500 VDC)
(f = 1 MHz)
VISO
RISO
CISO
2500
1011
VRMS
Ω
2
pF
DESCRIPTION / APPLICATIONS
The input of the MID400 consists of two back-to-back LED diodes which will accept and convert alternating currents into light
energy. An integrated photo diode-detector amplifier forms the output network. Optical coupling between input and output provides
2500 VRMS voltage isolation. A very high current transfer ratio (defined as the ratio of the DC output current and the DC input cur-
rent) is achieved through the use of high gain amplifier. The detector amplifier circuitry operates from a 5 V DC supply and drives
an open collector transistor output. The switching times are intentionally designed to be slow in order to enable the MID400, when
used as an AC line monitor, to respond only to changes in input voltage exceeding many milliseconds. The short period of time
during zero-crossing which occurs once every half cycle of the power line is completely ignored. To operate the MID400, always
add a resistor, RIN, in series with the input (as shown in test circuit 1) to limit the current to the required value. The value of the
resistor can be determined by the following equation:
RIN
=
V-----I--N-----–----V-----F-
IIN
Where VIN (RMS) is the input voltage.
VF is the forward voltage drop across the LED.
IIN (RMS) is the desired input current required to sustain a logic “O” on the output.
PIN DESCRIPTION
DESIGNATION
VIN1, VIN2
VCC
AUX.
PIN #
1,3
8
7
VO
6
GND
5
FUNCTION
Input terminals
Supply voltage, output circuit.
Auxiliary terminal.
Programmable capacitor input to
adjust AC voltage sensing level and
time delay.
Output terminal; open collector.
Circuit ground potential.
© 2003 Fairchild Semiconductor Corporation
Page 4 of 11
SCHEMATIC DIAGRAM
VIN1 1
2
VIN2 3
4
8 VCC
7 AUX.
6 VO
5 GND
NOTE: DO NOT CONNECT PINS 2 AND 4
7/24/03
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