SMM150 Просмотр технического описания (PDF) - Summit Microelectronics
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SMM150 Datasheet PDF : 22 Pages
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INTERNAL BLOCK DIAGRAM
READY
FAULT#
SMM150
Preliminary Information
VDD
VDD_CAP
GND
VREF =
1.25V or 0.5V
VREF
50kΩ
Output
Control
Glitch
Filter
OV/UV
VREF
COMP1
OV/UV
COMP2
Up/Dn
MUP
MDN
Margin
Target
Digital
Comparator
Control
Logic
8-bit DAC
Halt
SW1
50kΩ
Clock
TRIM
A0
A1
A2
I2C
SCL
Interface
SDA
10Bit
ADC
MUX
VM
SW2
WP
EE
Configuration
CAPM
Registers
& Memory
Figure 2 – SMM150 Controller Internal Block Diagram.
PACKAGE AND PIN CONFIGURATION
28 Pad QFN
Top View
20 Ball Ultra CSPTM
Bottom View
Pin 1
28 27 26 25 24 23 22
SCL 1
A2 2
NC 3
A1 4
READY 5
A0 6
GND 7
GND
SMoMr 150
NC
21 VDD
20 TRIM
19 COMP1
18 NC
17 NC
16 NC
15 NC
8 9 10 11 12 13 14
Pin 1
SCL MDN VDD_CAP VDD
A1 A2 A3 A4
A2
SDA TRIM COMP1
B1 B2 B3 B4
A1 READY MUP NC
C1 C2 C3 C4
A0
WP FAULT# NC
D1 D2 D3 D4
GND CAP_M COMP2 VM
E1 E2 E3 E4
Summit Microelectronics, Inc
2075 2.6 05/13/05
3
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