SSD1805 Просмотр технического описания (PDF) - Solomon Systech

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SSD1805

132 x 68 STN LCD Segment / Common Monochrome Driver with Controller

Solomon Systech  

7 FUNCTIONAL BLOCK DESCRIPTIONS

7.1 Microprocessor Interface Logic

The Microprocessor Interface unit consists of three functional blocks for driving the 6800-series parallel

interface, 8080-series parallel interface and 4-wires serial peripheral interface. The selection of different

interfaces is done by P/ S pin and C68/ 80 pin. Please refer to the pin descriptions on page 8.

a) MPU 6800-series Parallel Interface

The parallel interface consists of 8 bi-directional data pins (D7-D0), R/W ( WR ), D/ C , E( RD ),

CS 1 and CS2. R/W ( WR ) input high indicates a read operation from the Graphic Display Data

RAM (GDDRAM) or the status register. R/ W ( WR ) input Low indicates a write operation to

Display Data RAM or Internal Command Registers depending on the status of D/ C input. The

E( RD ) input serves as data latch signal (clock) when high provided that CS 1 and CS2 are low

and high respectively. Please refer to Figure 11 & 12 on page 40 & 41 for Parallel Interface

Timing Diagram of 6800-series microprocessors. In order to match the operating frequency of the

GDDRAM with that of the MCU, some pipeline processing is internally performed which requires

the insertion of a dummy read before the first actual display data read. This is shown in Figure 3.

R/W (W R)

E (RD)

data bus

N

write column address

dummy read

n

data read1

n+1

data read 2

n +2

data read 3

Figure 3 - Display Data Read with the insertion of dummy read

b) MPU 8080-series Parallel Interface

The parallel interface consists of 8 bi-directional data pins (D7-D0), E( RD ), R/W ( WR ), D/ C ,

CS 1 and CS2. E( RD ) input serves as data read latch signal (clock) when low provided that CS 1

and CS2 are low and high respectively. Whether reading the display data from GDDRAM or

reading the status from status register is controlled by D/ C . R/W ( WR ) input serves as data write

latch signal (clock) when low provided that CS 1 and CS2 are low and high respectively. Whether

writing the display data to the GDDRAM or writing the command to the command register is

controlled by D/ C . A dummy read is also required before the first actual display data read for

8080-series interface. Please refer to figure 13 & 14 on page 42 & 43 for Parallel Interface Timing

Diagram of 8080-series microprocessors.

c) MPU 4-wires Serial Interface

The 4-wires serial interface consists of serial clock SCK (D6), serial data SDA (D7), D/ C , CS 1

and CS2. SDA is shifted into a 8-bit shift register on every rising edge of SCK in the order of data

bit 7, data bit 6, …, data bit 0. D/ C is sampled on every eighth clock to determine whether the

data byte in the shift register is written to the Display Data RAM or command register at the same

clock. Please refer to figure 15 & 16 on page 43 & 44 for serial interface timing.

Remarks: For SPI mode, it is necessary to add one time of software reset command (code: E2) in

the first line of the initialization code.

Solomon Systech

Jun 2004 P 16/52 Rev 1.1 SSD1805 Series

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