SX1781 Просмотр технического описания (PDF) - Semtech Corporation
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SX1781 Datasheet PDF : 16 Pages
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SX1781
PLL Frequency Synthesizer with integrated VCO
ADVANCED COMMUNICATIONS & SENSING
FINAL
DATASHEET
6. Serial Interface: Slave SPI
The device is configured with a serial microprocessor bus. Figure 1 and Figure 2 show the timing diagrams of write and
read accesses. The serial interface is SPI compatible with a 16-bit word. The serial interface clock (SCK) is not required to
run between accesses (i.e., when CSB = 1).
6.1. Read Register
To read the value of a configuration register the timing diagram below should be carefully followed by the uC.
Figure 1. Read Register Timing
When reading more than one register successively, it is not compulsory to toggle CSB back high between two cycles. The
bytes are alternatively considered as address and value.
MOSI: Master latches the address bit value on SCK falling edge and Slave samples the data on rising edge of SCK.
MISO: Slave latches the register bit value on falling edge of SCK and Master samples the value on the next rising edge.
Table 8 SPI Read Timings
Parameter
SPI Clock Frequency
Setup MOSI valid to SCKrising edge
Setup CSB falling edge to SCKrising edge
Delay SCKfalling edge to MISO valid
Delay CSBrising edge to MISO high-Z
SCK Low time
SCK High time
Hold MOSI valid after SCKrising edge
Hold CSB Low after SCKrising edge
Time between two accesses (CSBrising edge to CSBfalling edge)
Symbol
Fsck
tsdata
tscsb
td1
td2
tcl
tch
thdata
thcsb
tp
Minimum
-
4
Typical
-
-
Maximum
20
-
14
-
-
-
-
25
-
25
-
25
-
-
25
-
-
6
-
-
6
-
-
25
-
-
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev 1 - November 2008
©2008 Semtech Corp.
Page 7
www.semtech.com
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