Figure 10. Enable Timing (1)
Dem_out
ENABLE
DATA
Sleep mode
IS = I Soff
Figure 11. Enable Timing (2)
Start-up mode
IS = I Son
T
Start-up
tee_sig
Receiving mode
IS = I Son
Dem_out
ENABLE
DATA
Sleep mode
IS = I Soff
Start-up mode
IS = I Son
T
Start-up
t
ee_sig
Receiving mode
IS = I Son
Digital Signal
Processing
The data from the ASK demodulator (Dem_out) is digitally processed in different ways
and as a result converted into the output signal DATA. This processing depends on the
selected baudrate range (BR_Range). Figure 12 illustrates how Dem_out is synchro-
nized by the extended basic clock cycle TXClk. Data can change its state only after TXClk
has elapsed. The edge-to-edge time period tee_sig of the DATA signal as a result is
always an integral multiple of TXClk.
The minimum time period between two edges of the data signal is limited to tee_sig ³
TDATA_min. This implies an efficient suppression of spikes at the DATA output. At the
same time it limits the maximum frequency of edges at DATA. This eases the interrupt
handling of a connected microcontroller.
10 T5744
4521B–RKE–01/03