TDA3608TH Просмотр технического описания (PDF) - Philips Electronics
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TDA3608TH Datasheet PDF : 22 Pages
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Philips Semiconductors
Multiple voltage regulators with switch
Product specification
TDA3608Q; TDA3608TH
SYMBOL
PARAMETER
Iq
SVRR
quiescent current
supply voltage ripple
rejection
Vdrop
dropout voltage
Im
current limit
Isc
short-circuit current
Power switch
Vdrop
dropout voltage
Vcl
clamping voltage
Vfb
flyback voltage
behaviour
Idc
continuous current
IM
peak current
Isc
short-circuit current
CONDITIONS
IREG3 = 400 mA
fi = 3 kHz; Vi = 2 V (p-p)
VP = 5.75 V; IREG3 = 400 mA;
note 7
VREG3 > 4.5 V; see Fig.10;
note 8
RL ≤ 0.5 Ω; see Fig.10; note 9
ISW = 1 A; note 12
ISW = 1.8 A; note 12
VP ≥ 18 V
ISW = −100 mA
VP = 16 V; VSW = 13.5 V
VP = 17 V; see Fig.11; note 13
VP = 14.4 V; VSW < 3.5 V;
see Fig.11; note 14
MIN.
−
60
TYP.
15
70
−
1
0.45 0.70
100 400
−
0.45
−
1.0
15
16.2
−
VP + 3
1.8 2.0
2
−
−
0.5
MAX.
40
−
1.5
−
−
UNIT
mA
dB
V
A
mA
0.7
V
1.8
V
17.2
V
22
V
−
A
−
A
−
A
Backup switch
Idc
continuous current
0.3 0.35
−
A
Vcl
clamping voltage
VP ≥ 16.7 V
−
−
16
V
Ir
reverse current
VP = 0; VBU = 12.4 V; note 15 −
−
900
mA
Notes
1. The minimum value is the minimum operating voltage, only if VP has exceeded 6.5 V.
2. The quiescent current is measured in the standby mode. Therefore, the enable inputs of regulator 1, regulator 3 and
the power switch are grounded and RL(REG2) = ∞.
3. The voltage of the regulator drops as a result of a VP drop.
4. The rise and fall time is measured with a 10 kΩ pull-up resistor and CL = 50 pF.
5. This is the threshold voltage for the delay time of the power switch. The voltage on the reset delay capacitor increases
only at low output voltage of the power switch (for example at short circuit). When the voltage on this capacitor
exceeds this threshold voltage, the power switch is set to the foldback mode. The power switch is also protected by
the temperature protection.
6. Delay time calculation:
a) Reset pulse delay: td(res) = I--Cc---h- × VC(th1) = C × 1000 × 103 [sec] The delay time is 47 ms for C = 47 nF.
b) Power switch delay: td(sw) = -I-Cc---h- × VC(th2) = C × 500 × 103 [sec] The delay time is 23.5 ms for C = 47 nF.
7. The dropout voltage of regulator 1, regulator 2 and regulator 3 is measured between pin VP and pins REG1, REG2
or REG3 respectively.
8. During current limit, current Im is held constant.
9. The foldback current protection limits the dissipated power at short-circuit.
2003 Nov 28
12
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