N80C51GB Просмотр технического описания (PDF) - Intel

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N80C51GB

CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

Intel 

8XC51GB

DC CHARACTERISTICS (Over Operating Conditions) (Continued)

Symbol

Parameter

Min

Typ(1) Max

VOH

VOH1

IIL

Output High Voltage

(Ports 1 2 3 4 and 5

ALE PSEN)

Output High Voltage

(Port 0 in External

Bus Mode)

Logical 0 Input Current

(Ports 1 2 3 4 5)

VCC b 0 3

VCC b 0 7

VCC b 1 5

VCC b 0 3

VCC b 0 7

VCC b 1 5

b50

ITL

Logical 1-to-0 Transition

Current (Ports 1 2 3 4 5)

b650

ILI

Input Leakage Current

(Port 0)

g10

RRST

RST Pullup Resistor

50

300

CIO

Pin Capacitance

10

IPD

Power Down Current

50

IDL

Idle Mode Current

18

ICC

Operating Current 16 MHz

50

IREF

A D Converter Reference

5

Current

Unit

V

V

V

V

V

V

mA

mA

mA

kX

pF

mA

mA

mA

mA

Test Conditions

IOH e b10 mA (4)

IOH e b30 mA (4)

IOH e b60 mA (4)

IOH e b200 mA

IOH e b3 2 mA

IOH e b7 0 mA

VIN e 0 45V

VIN e 2 0V

0 45 k VIN k VCC

Freq e 1 MHz

TA e 25 C

(5)

(5)

(5)

NOTES

1 Typical values are obtained using VCC e 5 0V TA e 25 C and are not guaranteed

2 Under steady state (non-transient) conditions IOL must be externally limited as follows

Maximum IOL per Port Pin

10 mA

Maximum IOL per 8-Bit Port

Port 0

26 mA

Ports 1–5

15 mA

Maximum Total IOL for All Outputs Pins 101 mA

If IOL exceeds the test conditions VOL may exceed the related specification Pins are not guaranteed to sink current

greater than the listed test conditions

3 Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0 4V on the low level outputs of ALE and

Ports 1 2 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins

change from 1 to 0 In applications where capacitive loading exceeds 100 pF the noise pulses on these signals may exceed

0 8V It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic

4 Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0 9 VCC specification when the

address lines are stabilizing

5 See Figures 6 – 10 for test conditions Minimum VCC for Power Down is 2V

9

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