QL6250-4PS484I Просмотр технического описания (PDF) - QuickLogic Corporation
Номер в каталоге
Компоненты Описание
производитель
QL6250-4PS484I Datasheet PDF : 73 Pages
| |||
Eclipse Family Data Sheet Rev. F
Table 10: DC Characteristics
Symbol
Parameter
II
I or I/O Input Leakage Current
IOZ
3-State Output Leakage Current
CI
Input Capacitancea
IOS
Output Short Circuit Currentb
ICC
ICCIO
ICCIO(DIF)
D.C. Supply Currentc
D.C. Supply Current on VCCIO
D.C. Supply Current on VCCIO
for Differential I/O
IREF
D.C. Supply Current on INREF
IPD
Pad Pull-down (programmable)
Conditions
VI = VCCIO or GND
VI = VCCIO or GND
-
Vo = GND
Vo = VCC
VI,Vo = VCCIO or GND
-
-
-
VCCIO = 3.6 V
Min.
-10
-10
-
-15
40
0.50 (typ)
0
-
-10
-
a. Capacitance is sample tested only. Clock pins are 12 pF maximum.
b. Only one output at a time. Duration should not exceed 30 seconds.
c. For -4/-5/-6/-7 commercial grade devices only. See Table 11 for more details on ICC characteristics.
Max.
10
10
8
-180
210
2
2
-
10
150
Unit
µA
µA
pF
mA
mA
mA
mA
mA
µA
µA
Table 11: ICC Characteristics
Characteristic
Condition
Commercial
Temperature
Industrial
Military
ICC
VCCPLL = GND
VCCPLL = VCC
2 mA (max)
3.25 mA (max)
3 mA (max)
5 mA (max)
5 mA (max)
10 mA (max)
NOTE: If PLLs are not used, the VCCPLL and PLLRST pins may be grounded to the lower ICC for the device.
Table 12: DC Input and Output Levels
INREF
VIL
VIH
VOL
VOH
IOL IOH
VMIN VMAX VMIN
VMAX
VMIN
VMAX
VMAX
VMIN
mA mA
LVTTL n/a n/a -0.3
0.8
2.0
VCCIO + 0.3
0.4
2.4
2.0 -2.0
LVCMOS2 n/a n/a -0.3
0.7
1.7
VCCIO + 0.3
0.7
1.7
2.0 -2.0
GTL+ 0.88 1.12 -0.3 INREF - 0.2 INREF + 0.2 VCCIO + 0.3
0.6
n/a
40 n/a
PCI
n/a n/a -0.3 0.3 x VCCIO 0.5 x VCCIO VCCIO + 0.5 0.1 x VCCIO 0.9 x VCCIO 1.5 -0.5
SSTL2 1.15 1.35 -0.3 INREF - 0.18 INREF + 0.18 VCCIO + 0.3
0.74
1.76 7.6 -7.6
SSTL3 1.3 1.7 -0.3 INREF - 0.2 INREF + 0.2 VCCIO + 0.3
1.10
1.90
8 -8
NOTE: The data provided in Table 12 are JEDEC and PCI Specifications. QuickLogic devices either meet
or exceed these requirements.
NOTE: All dedicated inputs including the CLK, DEDCLK, PLLIN, PLLRST, and IOCTRL pins, are clamped
to the VCC rail, not the VCCIO. Therefore, these pins can only be driven up to VCC + 0.3 V. These input pins
are LVCMOS2 compliant only (2.5 V).
© 2007 QuickLogic Corporation
www.quicklogic.com
•
•••
••
19
Share Link: 