QL6250-4PS484I Просмотр технического описания (PDF) - QuickLogic Corporation

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QL6250-4PS484I

Combining performance,density, and embedded RAM.

QuickLogic Corporation 

Eclipse Family Data Sheet Rev. F

PLL Signals

Table 5 summarizes the key signals in QuickLogic PLLs.

Table 5: PLL Signals

Signal Name

PLLCLK_INa Input clock signal

Description

PLLRST

Active High Reset If PLLRST is asserted, then CLKNET_OUT and PLLPAD_OUT are reset to 0.

This signal must be asserted and then released in order for the LOCK_DETECT to work.

ONn_OFFCHIP

PLL output This signal selects whether the PLL will drive the internal clock network or be used off-

chip. This is a static signal, not a dynamic signal.

Tied to GND = outgoing signal drives internal gates.

Tied to VCC = outgoing signal used off-chip.

CLKNET_OUT

Out to internal gates This signal bypasses the PLL logic before driving the internal gates. Note that

this signal cannot be used in the same quadrant where the PLL signal is used (PLLCLK_OUT).

PLLCLK_OUT

Out from PLL to internal gates This signal can drive the internal gates after going through the PLL.

For this to work, ONn_OFFCHIP must be tied to GND.

PLLPAD_OUT

Out to off-chip This outgoing signal is used off-chip. For this to work, ONn_OFFCHIP signal must

be tied to VCC.

Active High Lock detection signal NOTE: For simulation purposes, this signal gets asserted after

LOCK_DETECT 10 clock cycles. However, it can take a maximum of 200 clock cycles to sync with the input clock

upon release of the RESET signal.

a. Because PLLCLK_IN and PLLRST signals have INPAD, and PLLPAD_OUT has OUTPAD, you do not have to add additional pads

to your design.

NOTE: For PLL AC specifications, contact the factory.

© 2007 QuickLogic Corporation

www.quicklogic.com

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