UPC4093 Просмотр технического описания (PDF) - NEC => Renesas Technology

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Компоненты Описание

производитель

UPC4093

J-FET INPUT LOW-OFFSET OPERATIONAL AMPLIFIER

NEC => Renesas Technology 

PACKAGE DRAWINGS

8PIN PLASTIC DIP (300 mil)

8

5

µPC4093

1

4

A

K

I

P

L

J

H

C

G

B

M

R

F

D

NM

NOTES

1) Each lead centerline is located within 0.25 mm (0.01 inch) of

its true position (T.P.) at maximum material condition.

2) ltem "K" to center of leads when formed parallel.

ITEM MILLIMETERS INCHES

A

10.16 MAX. 0.400 MAX.

B

1.27 MAX.

0.050 MAX.

C

2.54 (T.P.) 0.100 (T.P.)

D

0.50±0.10

0.020

+0.004

–0.005

F

1.4 MIN.

0.055 MIN.

G

3.2±0.3

0.126±0.012

H

0.51 MIN.

0.020 MIN.

I

4.31 MAX.

0.170 MAX.

J

5.08 MAX.

0.200 MAX.

K

7.62 (T.P.) 0.300 (T.P.)

L

6.4

0.252

M

0.25+–00..0150

0.010

+0.004

–0.003

N

0.25

0.01

P

0.9 MIN.

0.035 MIN.

R

0~15°

0~15°

P8C-100-300B,C-1

6

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