UPD16663N Просмотр технического описания (PDF) - NEC => Renesas Technology

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производитель

UPD16663N

240-OUTPUT LCD COLUMN (SEGMENT) DRIVER WITH BUILT-IN RAM

NEC => Renesas Technology 

µPD16663

10. LCD TIMING GENERATOR CIRCUIT

If master mode is entered by setting MS to H, /FRM and STB are generated at a timing that is 1/160 of the duty

ratio, and driver voltage selection signals L1 and L2 are generated for the row driver.

/FRM is generated twice per frame, STB 81 times per 1/2 frame or 162 times per frame.

(1) /FRM, STB signal generation

OSC1

PULSE

STB

1

2

/FRM

STB

81

1

2

81

1

2

Frame

81

1

2

(2) L1, L2 signal generation

STB

1 2 3 4…1 2 3 4…1 2 3 4…1 2 3 4…

L1

1 1 1 1…1 1 1 1…0 0 0 0…0 0 0 0…

L2

1 0 1 0…0 1 0 1…0 1 0 1…1 0 1 0…

Data Sheet S13392EJ1V0DS00

21

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