PIN CONFIGURATIONS (TOP VIEW)
(1) Normal operating mode
• 80-PIN PLASTIC QFP (14 × 14 mm, 0.65-mm pitch)
µPD178P018AGC-3B9 Note
• 80-PIN CERAMIC WQFN (14 × 14 mm, 0.65-mm pitch)
µPD178P018AKK-T Note
µPD178P018A
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P20/SI1
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P132/PWM0
P133/PWM1
P134/PWM2
P40
P41
P42
180 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 6160
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
2021 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 4041
P37
P36/BEEP
P35
P34/TI2
P33/TI1
P32
P31
P30
P67
P66
P65
P64
P63
P62
P61
P60
P57
P56
P55
P54
Note Under development
Cautions 1. Connect the VPP pin to GND directly.
2. Connect the VDDPORT and VDDPLL pins to VDD.
3. Connect the GNDPORT and GNDPLL pins to GND.
4. Connect each of the REGOSC and REGCPU pins to GND via a 0.1-µF capacitor.
5