UPD4702G Просмотр технического описания (PDF) - NEC => Renesas Technology
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UPD4702G Datasheet PDF : 16 Pages
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µPD4702
1. DESCRIPTION OF OPERATIONS
(1) Count operation
The µPD4702 incorporates a phase discrimination circuit, and counts by 4-multiplication of the A and B input 2-
phase pulses. Therefore, a count operation is performed by an A input edge and a B input edge.
Fig. 1 Count Operation Timing Chart
Forward (Up-Count)
Reverse (Down-Count)
A Input
Count Operation
B Input
1
2
3
4
5
4
3
2
1
0
(2) Latch operation
An R-S flip-flop is inserted in the strobe input of the latch circuit as shown in Fig. 2, and when STB changes from
“H” to “L” during a count operation, the internal latch signal STB remains at “H” until the end of the count operation.
Therefore, the count value is latched correctly even if STB input is performed asynchronously from the A and B input
(if STB changes from “H” to “L” within tSABSTB (40 ns) after the A input or B input edge, the latch contents will be
either the pre-count or post-count value). However, when a µPD4704 is added, the correct value cannot be latched
if all digits are latched simultaneously when a carry or borrow is generated (the high-order digit may be latched
before carry/borrow transmission).
Fig. 2 STB Input Circuit
From Phase Discrimination Circuit
(Count Pulse)
STB
STB
Latched
when L
A, B Inputs
STB
tSABSTB
If tSABSTB is 40 ns or longer, the post-count value
is input to the latch.
3
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