Philips Semiconductors
16-bit bus transceiver with direction pin; 5V tolerant
(3-State)
Product specification
74LVC16245A/
74LVCH16245A
FEATURES
• 5 volt tolerant inputs/outputs for interfacing with 5V logic
• Wide supply voltage range of 1.2V to 3.6V
• Complies with JEDEC standard no. 8-1A
• CMOS low power consumption
• MULTIBYTETM flow-through standard pin-out architecture
• Low inductance multiple power and ground pins for minimum
noise and ground bounce
• Direct interface with TTL levels
• High impedance when VCC = 0
• All data inputs have bus hold (74LVCH16245A only)
PIN CONFIGURATION
1DIR 1
1B0 2
1B1 3
GND 4
1B2 5
1B3 6
VCC1 7
1B4 8
1B5 9
GND 10
48 1OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 VCC2
41 1A4
40 1A5
39 GND
DESCRIPTION
The 74LVC(H)16245A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families. Inputs can be driven from either
3.3V or 5V devices. In 3-State operation, outputs can handle 5V.
These features allow the use of these devices in a mixed 3.3V/5V
environment.
The 74LVC(H)16245A is a 16-bit transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
The 74LVC(H)16245A features two output enable (nOE) inputs for
easy cascading and two send/receive (nDIR) inputs for direction
control. nOE controls the outputs so that the buses are effectively
isolated. This device can be used as two 8-bit transceivers or one
16-bit transceiver.
The 74LVCH16245A bus hold data inputs eliminates the need for
extreme pull up resistors to hold unused inputs.
1B6 11
1B7 12
2B0 13
2B1 14
GND 15
2B2 16
2B3 17
VCC1 18
2B4 19
2B5 20
GND 21
2B6 22
2B7 23
2DIR 24
38 1A6
37 1A7
36 2A0
35 2A1
34 GND
33 2A2
32 2A3
31 VCC2
30 2A4
29 2A5
28 GND
27 2A6
26 2A7
25 2OE
SW00198
ORDERING INFORMATION
PACKAGES
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVC16245A DL
74LVC16245A DGG
74LVCH16245A DL
74LVCH16245A DGG
NORTH AMERICA
VC16245A DL
VC16245A DGG
VCH16245A DL
VCH16245A DGG
DWG NUMBER
SOT370-1
SOT362-1
SOT370-1
SOT362-1
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
Propagation delay
An to Bn;
Bn to An
CL = 50pF
VCC = 3.3V
CI
Input capacitance
CI/O
Input/output capacitance
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL × VCC2 × fo) = sum of the outputs.
TYPICAL
3.0
5.0
10
30
UNIT
ns
pF
pF
pF
1997 Sep 25
2
853-2013 18424