VP531ECG Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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VP531ECG Datasheet PDF : 17 Pages
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REFSQ
SC_SYNC
REFSQ
VP531E/VP551E
2:1 mux
0
fSC
Divide by 4
Synchronous Q
Counter
RESET
1
Input to
Genlocking
Block
FSC4_SEL
(register bit)
1/ f SC_SYNC
t PWH; SC_SYNC
tSU; SC_SYNC
SC_SYNC
t HD; SC_SYNC
Q
Figure 4 REFSQ and SC_SYNC input timing
Pixel Data Input (PD[7,0])
Sample Number
1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450
Y719 $FF $00 $00 $XY
ANCILLARY DATA...
EAV SEQUENCE
t SU; PD
t PWL; PXCK
PXCK Input (27MHz)
t PWH; PXCK
t HD; PD
t DUR; PAL_ID
t SU; PAL_ID
t HD; PAL_ID
D7 Input (PAL_ID)
PAL_ID Stable
Figure 5 PAL_ID input timing
11
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