Production Data
SERIAL INTERFACE
SCLK
DIN
NCS
1
tSUD
tHD
D15
tSUCSCK
tWL
tWH
2
3
D14
D13
Figure 1 Timing Diagram
WM2626
tSUC16CS
4
5 15
16
D12
D1
D0
Test Conditions:
RL = 10kΩ, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating
free-air temperature range (unless noted otherwise).
SYMBOL TEST CONDITIONS
MIN
tSUCSCK
Setup time, NCS low before first falling SCLK edge
10
Setup time, 16th falling SCLK edge (when data bit D0
tSUC16CS
is sampled) before NCS rising edge.
10
tWH
Pulse duration, SCLK high.
25
tWL
Pulse duration, SCLK low.
25
tSUD
Setup time, data ready before SCLK falling edge.
10
tHD
Hold time, data held valid after SCLK falling edge.
5
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
5