WM8951L
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD1, AVDD2, DBVDD = 3.3V, AGND1, AGND2 = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz,
XTI/MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
0.3 x DBVDD
V
Input HIGH level
VIH
Output LOW
VOL
0.7 x DBVDD
V
0.10 x
V
DBVDD
Output HIGH
VOH
0.9 x DBVDD
V
Power On Reset Threshold (DCVDD)
DCVDD Threshold On -> Off
Vth
0.9
V
Hysteresis
VIH
DCVDD Threshold Off -> On
VOL
Analogue Reference Levels
0.3
V
0.6
V
Reference voltage (VMID)
Potential divider resistance
VVMID
RVMID
AVDD1/2
V
50k
Ω
Line Input to ADC
Input Signal Level (0dB)
VINLINE
1.0
AVDD/3.3
Vrms
Signal to Noise Ratio
SNR
AVDD1/2= DBVDD=1.8V
75
85
dB
(Note 1,3)
DR
DCVDD=1.5V
dB
Dynamic Range (Note 3)
A-weighted, 0dB gain
@ fs = 48kHz
AVDD1/2= DBVDD=1.8V
85
DCVDD=1.5V
A-weighted, 0dB gain
@ fs = 96kHz
AVDD1/2= DBVDD=1.8V
80
88
DCVDD=1.5V
A-weighted, -60dB full
scale input
Total Harmonic Distortion
THD
AVDD1/2= DBVDD=1.8V
-76
-60
dB
DCVDD=1.5V
-1dB input, 0dB gain
Signal to Noise Ratio
SNR
AVDD1/2= DBVDD=1.8V
75
85
dB
(Note 1,3)
DCVDD=1.5V
A-weighted, 0dB gain
@ fs = 48kHz
Power Supply Rejection Ratio
PSRR
1kHz, 100mVpp
50
dB
20Hz to 20kHz,
45
100mVpp
ADC channel separation
1kHz input
90
dB
Programmable Gain
1kHz input
-34.5
0
+12
dB
Rsource < 50 Ohms
Programmable Gain Step Size
Guaranteed Monotonic
1.5
dB
Mute attenuation
0dB, 1kHz input
80
dB
Input Resistance
RINLINE
0dB gain
20k
30k
Ω
12dB gain
10k
15k
Input Capacitance
CINLINE
10
pF
Microphone Input to ADC @ 0dB Gain, fs = 48kHz (40kΩ Source Impedance. See Figure 11)
Input Signal Level (0dB)
VINMIC
1.0
AVDD/3.3
Vrms
w
PD Rev 4.0 May 2005
6